Comparison analysis on scaling the vertical and lateral NMOSFET in nanometer regime
Conventional lateral and vertical n-channel MOS transistors with channel length in the range of 100 nm to 50 nm have been systematically investigated by means of device simulation. The comparison analysis includes critical parameters that govern device performance. Threshold voltage VT roll-off, lea...
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| Language: | en |
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UKM
2008
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| Online Access: | http://eprints.utm.my/7507/3/RazaliIsmail2008_ComparisonAnalysisonScaling.pdf http://eprints.utm.my/7507/ http://pkukmweb.ukm.my/~jsm/english_journals/vol37num3_2008/contentsVol37num3_2008.html |
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| _version_ | 1845471822178418688 |
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| author | Saad, Ismail Sulaiman, Ima Ismail, Razali |
| author_facet | Saad, Ismail Sulaiman, Ima Ismail, Razali |
| author_sort | Saad, Ismail |
| building | UTM Library |
| collection | Institutional Repository |
| content_provider | Universiti Teknologi Malaysia |
| content_source | UTM Institutional Repository |
| continent | Asia |
| country | Malaysia |
| description | Conventional lateral and vertical n-channel MOS transistors with channel length in the range of 100 nm to 50 nm have been systematically investigated by means of device simulation. The comparison analysis includes critical parameters that govern device performance. Threshold voltage VT roll-off, leakage current Ioff drain saturation current IDsat and sub-threshold swing S were analyze and compared between the device. Due to double gate (DG) structure over the side of silicon pillar a better electrostatics potential control of channel is obtained in vertical device shown by an analysis on VT roll-off. A two decade higher of Ioff in planar device is observed with Lg = 50 nm. A factor of three times larger IDsat is observed for vertical MOSFETs compared to planar device. The sub-threshold swing S remains almost the same when the Lg larger than 80 nm. It increased rapidly when the Lg is scaled down to 50 nm due to the short channel effect SCE. However, the vertical device has a steady increase whereas the planar device has suffered immediate enhance of SCE. The analysis results confirmed that vertical MOSFET with double-gate structure is a potential solution to overcome SCE when scaled the channel length to 50 nm and beyond. |
| format | Article |
| id | my.utm.eprints-7507 |
| institution | Universiti Teknologi Malaysia |
| language | en |
| publishDate | 2008 |
| publisher | UKM |
| record_format | eprints |
| spelling | my.utm.eprints-75072017-02-13T04:19:50Z http://eprints.utm.my/7507/ Comparison analysis on scaling the vertical and lateral NMOSFET in nanometer regime Saad, Ismail Sulaiman, Ima Ismail, Razali TK Electrical engineering. Electronics Nuclear engineering Conventional lateral and vertical n-channel MOS transistors with channel length in the range of 100 nm to 50 nm have been systematically investigated by means of device simulation. The comparison analysis includes critical parameters that govern device performance. Threshold voltage VT roll-off, leakage current Ioff drain saturation current IDsat and sub-threshold swing S were analyze and compared between the device. Due to double gate (DG) structure over the side of silicon pillar a better electrostatics potential control of channel is obtained in vertical device shown by an analysis on VT roll-off. A two decade higher of Ioff in planar device is observed with Lg = 50 nm. A factor of three times larger IDsat is observed for vertical MOSFETs compared to planar device. The sub-threshold swing S remains almost the same when the Lg larger than 80 nm. It increased rapidly when the Lg is scaled down to 50 nm due to the short channel effect SCE. However, the vertical device has a steady increase whereas the planar device has suffered immediate enhance of SCE. The analysis results confirmed that vertical MOSFET with double-gate structure is a potential solution to overcome SCE when scaled the channel length to 50 nm and beyond. UKM 2008-09 Article PeerReviewed application/pdf en http://eprints.utm.my/7507/3/RazaliIsmail2008_ComparisonAnalysisonScaling.pdf Saad, Ismail and Sulaiman, Ima and Ismail, Razali (2008) Comparison analysis on scaling the vertical and lateral NMOSFET in nanometer regime. Sains Malaysiana, 37 (3). pp. 239-243. ISSN 0126-6039 http://pkukmweb.ukm.my/~jsm/english_journals/vol37num3_2008/contentsVol37num3_2008.html |
| spellingShingle | TK Electrical engineering. Electronics Nuclear engineering Saad, Ismail Sulaiman, Ima Ismail, Razali Comparison analysis on scaling the vertical and lateral NMOSFET in nanometer regime |
| title | Comparison analysis on scaling the vertical and lateral NMOSFET in nanometer regime |
| title_full | Comparison analysis on scaling the vertical and lateral NMOSFET in nanometer regime |
| title_fullStr | Comparison analysis on scaling the vertical and lateral NMOSFET in nanometer regime |
| title_full_unstemmed | Comparison analysis on scaling the vertical and lateral NMOSFET in nanometer regime |
| title_short | Comparison analysis on scaling the vertical and lateral NMOSFET in nanometer regime |
| title_sort | comparison analysis on scaling the vertical and lateral nmosfet in nanometer regime |
| topic | TK Electrical engineering. Electronics Nuclear engineering |
| url | http://eprints.utm.my/7507/3/RazaliIsmail2008_ComparisonAnalysisonScaling.pdf http://eprints.utm.my/7507/ http://pkukmweb.ukm.my/~jsm/english_journals/vol37num3_2008/contentsVol37num3_2008.html |
| url_provider | http://eprints.utm.my/ |