130 nm low power CMOS analog multiplier
Processing analog signal often involves analog multiplier and the multiplier is part of system on chip (SoC). Designing such system with a low power consumption is crucial nowadays. It is very important to increase the system battery lifetime. The design also must be smaller in size. In order to red...
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| Language: | en |
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IOP Publishing
2018
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| Online Access: | http://eprints.uthm.edu.my/2901/1/AJ%202019%20%2864%29.pdf http://eprints.uthm.edu.my/2901/ https://iopscience.iop.org/article/10.1088/1742-6596/1049/1/012071 |
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| _version_ | 1833417195978227712 |
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| author | Abu Naim, Ahmad Safuan Ruslan, Siti Hawa |
| author_facet | Abu Naim, Ahmad Safuan Ruslan, Siti Hawa |
| author_sort | Abu Naim, Ahmad Safuan |
| building | UTHM Library |
| collection | Institutional Repository |
| content_provider | Universiti Tun Hussein Onn Malaysia |
| content_source | UTHM Institutional Repository |
| continent | Asia |
| country | Malaysia |
| description | Processing analog signal often involves analog multiplier and the multiplier is part of system on chip (SoC). Designing such system with a low power consumption is crucial nowadays. It is very important to increase the system battery lifetime. The design also must be smaller in size. In order to reduce the power consumption of the multiplier, an architecture that require smaller current must be designed and the approach is to use a design that is able to function at a low voltage supply. This project has designed the analog multiplier with a low power consumption using Silterra 130 nm Complementary Metal Oxide Semiconductor (CMOS) technology. A four quadrant technique is applied in the design. The scaling of transistor will help in reducing the size of the analog multiplier, and the proposed circuit architecture has produced a compact multiplier. Cadence electronic design automation (EDA) Tools is used to design the circuit. The schematic, layout, physical verification and parasitic extraction with post layout simulation are done to verify the multiplier circuit is functioning. The analog multiplier is operated with 1.2 V voltage supply and the power consumption is 98 μW. At 1 V, the power consumption is 32 μW. The total area for the design is 99 μm². |
| format | Article |
| id | my.uthm.eprints-2901 |
| institution | Universiti Tun Hussein Onn Malaysia |
| language | en |
| publishDate | 2018 |
| publisher | IOP Publishing |
| record_format | eprints |
| spelling | my.uthm.eprints-29012021-11-16T04:05:10Z http://eprints.uthm.edu.my/2901/ 130 nm low power CMOS analog multiplier Abu Naim, Ahmad Safuan Ruslan, Siti Hawa TK5101-6720 Telecommunication. Including telegraphy, telephone, radio, radar, television Processing analog signal often involves analog multiplier and the multiplier is part of system on chip (SoC). Designing such system with a low power consumption is crucial nowadays. It is very important to increase the system battery lifetime. The design also must be smaller in size. In order to reduce the power consumption of the multiplier, an architecture that require smaller current must be designed and the approach is to use a design that is able to function at a low voltage supply. This project has designed the analog multiplier with a low power consumption using Silterra 130 nm Complementary Metal Oxide Semiconductor (CMOS) technology. A four quadrant technique is applied in the design. The scaling of transistor will help in reducing the size of the analog multiplier, and the proposed circuit architecture has produced a compact multiplier. Cadence electronic design automation (EDA) Tools is used to design the circuit. The schematic, layout, physical verification and parasitic extraction with post layout simulation are done to verify the multiplier circuit is functioning. The analog multiplier is operated with 1.2 V voltage supply and the power consumption is 98 μW. At 1 V, the power consumption is 32 μW. The total area for the design is 99 μm². IOP Publishing 2018 Article PeerReviewed text en http://eprints.uthm.edu.my/2901/1/AJ%202019%20%2864%29.pdf Abu Naim, Ahmad Safuan and Ruslan, Siti Hawa (2018) 130 nm low power CMOS analog multiplier. Journal of Physics: Conference Series (JPCS), 1049. pp. 1-8. ISSN 1742-6588 https://iopscience.iop.org/article/10.1088/1742-6596/1049/1/012071 |
| spellingShingle | TK5101-6720 Telecommunication. Including telegraphy, telephone, radio, radar, television Abu Naim, Ahmad Safuan Ruslan, Siti Hawa 130 nm low power CMOS analog multiplier |
| title | 130 nm low power CMOS analog multiplier |
| title_full | 130 nm low power CMOS analog multiplier |
| title_fullStr | 130 nm low power CMOS analog multiplier |
| title_full_unstemmed | 130 nm low power CMOS analog multiplier |
| title_short | 130 nm low power CMOS analog multiplier |
| title_sort | 130 nm low power cmos analog multiplier |
| topic | TK5101-6720 Telecommunication. Including telegraphy, telephone, radio, radar, television |
| url | http://eprints.uthm.edu.my/2901/1/AJ%202019%20%2864%29.pdf http://eprints.uthm.edu.my/2901/ https://iopscience.iop.org/article/10.1088/1742-6596/1049/1/012071 |
| url_provider | http://eprints.uthm.edu.my/ |