Hardware Implementation of FIR Filter for ECG Signal Processing: Design, Optimization, and Performance Analysis on an FPGA
Electrocardiogram (ECG) signals are commonly used to diagnose heart-related diseases. However, noise induced during the measurement process can affect the accuracy of the diagnosis. Digital filters, such as the Finite Impulse Response (FIR) filter, are widely used to filter out noise from the ECG si...
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semarak ilmu
2024
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| Online Access: | http://eprints.uthm.edu.my/11009/1/J17512_cc75d5ba068fb25264836491ff199252.pdf http://eprints.uthm.edu.my/11009/ https://doi.org/10.37934/araset.40.2.5061 |
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| author | Chessda Uttraphan, Chessda Uttraphan Ariffi Ardani, Mohd Izzul Chua Wee Heng, Chua Wee Heng Ahmad, Nabihah Kok Boon Ching, Kok Boon Ching A Arul Edwin Raj, A Arul Edwin Raj |
| author_facet | Chessda Uttraphan, Chessda Uttraphan Ariffi Ardani, Mohd Izzul Chua Wee Heng, Chua Wee Heng Ahmad, Nabihah Kok Boon Ching, Kok Boon Ching A Arul Edwin Raj, A Arul Edwin Raj |
| author_sort | Chessda Uttraphan, Chessda Uttraphan |
| building | UTHM Library |
| collection | Institutional Repository |
| content_provider | Universiti Tun Hussein Onn Malaysia |
| content_source | UTHM Institutional Repository |
| continent | Asia |
| country | Malaysia |
| description | Electrocardiogram (ECG) signals are commonly used to diagnose heart-related diseases. However, noise induced during the measurement process can affect the accuracy of the diagnosis. Digital filters, such as the Finite Impulse Response (FIR) filter, are widely used to filter out noise from the ECG signal. Nevertheless, the processing speed of software-based FIR filters is slow for large ECG datasets due to serial processing. This paper presents a hardware implementation of the FIR filter for ECG signal processing to overcome the processing speed issue. The filter is designed using the Kaiser Window method and implemented on the Intel Cyclone IV Field Programmable Gate Array (FPGA). The filter is first designed in MATLAB to obtain the filter coefficients where the ECG data were obtained from Physionet database. From the difference equation, we designed the signal flow graph (SDFG) and then mapped
into hardware logics to enable parallel processing. Simulation results of the software (MATLAB) and hardware (FPGA) implementations are obtained and compared. The results show that the FPGA-based FIR filter can process the ECG signal up to 1,250 times faster than software implementations. To further optimize the design and reduce hardware cost, we introduce optimized designs by applying the operation scheduling and constrained resource allocation techniques. The maximum operating frequency, logic utilization, and power consumption of each design were analysed and compared. This study demonstrates that custom-designed hardware logic for digital signal processing can significantly outperform software implementations due to its parallel
processing capabilities. The proposed optimization techniques reduce the hardware cost while maintaining high processing speed and accuracy. The hardware implementation of the FIR filter for ECG signal processing has numerous applications in diagnosing heart-related diseases and real-time monitoring of ECG signals in critical care settings. |
| format | Article |
| id | my.uthm.eprints-11009 |
| institution | Universiti Tun Hussein Onn Malaysia |
| language | en |
| publishDate | 2024 |
| publisher | semarak ilmu |
| record_format | eprints |
| spelling | my.uthm.eprints-110092024-05-29T02:22:18Z http://eprints.uthm.edu.my/11009/ Hardware Implementation of FIR Filter for ECG Signal Processing: Design, Optimization, and Performance Analysis on an FPGA Chessda Uttraphan, Chessda Uttraphan Ariffi Ardani, Mohd Izzul Chua Wee Heng, Chua Wee Heng Ahmad, Nabihah Kok Boon Ching, Kok Boon Ching A Arul Edwin Raj, A Arul Edwin Raj TA Engineering (General). Civil engineering (General) Electrocardiogram (ECG) signals are commonly used to diagnose heart-related diseases. However, noise induced during the measurement process can affect the accuracy of the diagnosis. Digital filters, such as the Finite Impulse Response (FIR) filter, are widely used to filter out noise from the ECG signal. Nevertheless, the processing speed of software-based FIR filters is slow for large ECG datasets due to serial processing. This paper presents a hardware implementation of the FIR filter for ECG signal processing to overcome the processing speed issue. The filter is designed using the Kaiser Window method and implemented on the Intel Cyclone IV Field Programmable Gate Array (FPGA). The filter is first designed in MATLAB to obtain the filter coefficients where the ECG data were obtained from Physionet database. From the difference equation, we designed the signal flow graph (SDFG) and then mapped into hardware logics to enable parallel processing. Simulation results of the software (MATLAB) and hardware (FPGA) implementations are obtained and compared. The results show that the FPGA-based FIR filter can process the ECG signal up to 1,250 times faster than software implementations. To further optimize the design and reduce hardware cost, we introduce optimized designs by applying the operation scheduling and constrained resource allocation techniques. The maximum operating frequency, logic utilization, and power consumption of each design were analysed and compared. This study demonstrates that custom-designed hardware logic for digital signal processing can significantly outperform software implementations due to its parallel processing capabilities. The proposed optimization techniques reduce the hardware cost while maintaining high processing speed and accuracy. The hardware implementation of the FIR filter for ECG signal processing has numerous applications in diagnosing heart-related diseases and real-time monitoring of ECG signals in critical care settings. semarak ilmu 2024 Article PeerReviewed text en http://eprints.uthm.edu.my/11009/1/J17512_cc75d5ba068fb25264836491ff199252.pdf Chessda Uttraphan, Chessda Uttraphan and Ariffi Ardani, Mohd Izzul and Chua Wee Heng, Chua Wee Heng and Ahmad, Nabihah and Kok Boon Ching, Kok Boon Ching and A Arul Edwin Raj, A Arul Edwin Raj (2024) Hardware Implementation of FIR Filter for ECG Signal Processing: Design, Optimization, and Performance Analysis on an FPGA. Journal of Advanced Research in Applied Sciences and Engineering Technology, 40 (2). pp. 50-61. ISSN 2462-1943 https://doi.org/10.37934/araset.40.2.5061 |
| spellingShingle | TA Engineering (General). Civil engineering (General) Chessda Uttraphan, Chessda Uttraphan Ariffi Ardani, Mohd Izzul Chua Wee Heng, Chua Wee Heng Ahmad, Nabihah Kok Boon Ching, Kok Boon Ching A Arul Edwin Raj, A Arul Edwin Raj Hardware Implementation of FIR Filter for ECG Signal Processing: Design, Optimization, and Performance Analysis on an FPGA |
| title | Hardware Implementation of FIR Filter for ECG Signal Processing: Design, Optimization, and Performance Analysis on an FPGA |
| title_full | Hardware Implementation of FIR Filter for ECG Signal Processing: Design, Optimization, and Performance Analysis on an FPGA |
| title_fullStr | Hardware Implementation of FIR Filter for ECG Signal Processing: Design, Optimization, and Performance Analysis on an FPGA |
| title_full_unstemmed | Hardware Implementation of FIR Filter for ECG Signal Processing: Design, Optimization, and Performance Analysis on an FPGA |
| title_short | Hardware Implementation of FIR Filter for ECG Signal Processing: Design, Optimization, and Performance Analysis on an FPGA |
| title_sort | hardware implementation of fir filter for ecg signal processing: design, optimization, and performance analysis on an fpga |
| topic | TA Engineering (General). Civil engineering (General) |
| url | http://eprints.uthm.edu.my/11009/1/J17512_cc75d5ba068fb25264836491ff199252.pdf http://eprints.uthm.edu.my/11009/ https://doi.org/10.37934/araset.40.2.5061 |
| url_provider | http://eprints.uthm.edu.my/ |