High-performance, fault-tolerant architecture for reliable hybrid nanolectronic memories
Although hybrid nanoelectronic memories (hybrid memories) promise scalability potentials such as ultrascale density and low power consumption, they are expected to suffer from high defect/fault density reducing their reliability. Such defects/faults can impact any part of the memory system including...
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Penerbit Universiti Teknikal Malaysia Melaka
2012
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| Online Access: | http://eprints.utem.edu.my/id/eprint/6764/1/JETC12_published.pdf http://eprints.utem.edu.my/id/eprint/6764/ https://jtec.utem.edu.my/jtec/article/view/430/299 |
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| author | Haron, Nor Zaidi Darsono, Abd Majid Awang Md Isa, Azmi |
| author_facet | Haron, Nor Zaidi Darsono, Abd Majid Awang Md Isa, Azmi |
| author_sort | Haron, Nor Zaidi |
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| collection | Institutional Repository |
| content_provider | Universiti Teknikal Malaysia Melaka |
| content_source | UTEM Institutional Repository |
| continent | Asia |
| country | Malaysia |
| description | Although hybrid nanoelectronic memories (hybrid memories) promise scalability potentials such as ultrascale density and low power consumption, they are expected to suffer from high defect/fault density reducing their reliability. Such defects/faults can impact any part of the memory system including the memory cell array, the encoder and the decoder. This article presents a high-performance, fault-tolerant architecture for hybrid memories; it is based on a combination of two techniques: (i) an error correction scheme that tolerates both random and clustered faults in memory cell array and (ii) an on-line masking incorporated into the decoder to tolerate faults in the decoder. Moreover, the decoding process is optimized for area and performance by reversing the decoding sequence. Experimental results show that the proposed architecture realizes a higher performance and competitive reliability level at a comparable overhead as compared with the state-of-the-art. For example, the architecture decodes 5× faster and provides 0.7% better reliability (assuming 10% fault rate) at the cost of similar area overhead (for 1024-bit memory word) as compared to Reed-Solomon code. |
| format | Article |
| id | my.utem.eprints-6764 |
| institution | Universiti Teknikal Malaysia Melaka |
| language | en |
| publishDate | 2012 |
| publisher | Penerbit Universiti Teknikal Malaysia Melaka |
| record_format | eprints |
| spelling | my.utem.eprints-67642023-05-30T12:21:20Z http://eprints.utem.edu.my/id/eprint/6764/ High-performance, fault-tolerant architecture for reliable hybrid nanolectronic memories Haron, Nor Zaidi Darsono, Abd Majid Awang Md Isa, Azmi TK Electrical engineering. Electronics Nuclear engineering Although hybrid nanoelectronic memories (hybrid memories) promise scalability potentials such as ultrascale density and low power consumption, they are expected to suffer from high defect/fault density reducing their reliability. Such defects/faults can impact any part of the memory system including the memory cell array, the encoder and the decoder. This article presents a high-performance, fault-tolerant architecture for hybrid memories; it is based on a combination of two techniques: (i) an error correction scheme that tolerates both random and clustered faults in memory cell array and (ii) an on-line masking incorporated into the decoder to tolerate faults in the decoder. Moreover, the decoding process is optimized for area and performance by reversing the decoding sequence. Experimental results show that the proposed architecture realizes a higher performance and competitive reliability level at a comparable overhead as compared with the state-of-the-art. For example, the architecture decodes 5× faster and provides 0.7% better reliability (assuming 10% fault rate) at the cost of similar area overhead (for 1024-bit memory word) as compared to Reed-Solomon code. Penerbit Universiti Teknikal Malaysia Melaka 2012-07 Article PeerReviewed text en http://eprints.utem.edu.my/id/eprint/6764/1/JETC12_published.pdf Haron, Nor Zaidi and Darsono, Abd Majid and Awang Md Isa, Azmi (2012) High-performance, fault-tolerant architecture for reliable hybrid nanolectronic memories. Journal of Telecommunication, Electronic and Computer Engineering, 4 (2). pp. 1-10. ISSN 2180-1843 https://jtec.utem.edu.my/jtec/article/view/430/299 |
| spellingShingle | TK Electrical engineering. Electronics Nuclear engineering Haron, Nor Zaidi Darsono, Abd Majid Awang Md Isa, Azmi High-performance, fault-tolerant architecture for reliable hybrid nanolectronic memories |
| title | High-performance, fault-tolerant architecture for reliable hybrid nanolectronic memories |
| title_full | High-performance, fault-tolerant architecture for reliable hybrid nanolectronic memories |
| title_fullStr | High-performance, fault-tolerant architecture for reliable hybrid nanolectronic memories |
| title_full_unstemmed | High-performance, fault-tolerant architecture for reliable hybrid nanolectronic memories |
| title_short | High-performance, fault-tolerant architecture for reliable hybrid nanolectronic memories |
| title_sort | high-performance, fault-tolerant architecture for reliable hybrid nanolectronic memories |
| topic | TK Electrical engineering. Electronics Nuclear engineering |
| url | http://eprints.utem.edu.my/id/eprint/6764/1/JETC12_published.pdf http://eprints.utem.edu.my/id/eprint/6764/ https://jtec.utem.edu.my/jtec/article/view/430/299 |
| url_provider | http://eprints.utem.edu.my/ |