On Defect Oriented Testing for Hybrid CMOS/memristor Memory
Hybrid CMOS/memristor memory (hybrid memory) technology is one of the emerging memory technologies potentially to replace conventional non-volatile flash memory. Existing research on such novel circuits focuses mainly on the integration between CMOS and non-CMOS, fabrication techniques and reliabili...
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| Format: | Conference or Workshop Item |
| Language: | en |
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2011
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| Online Access: | http://eprints.utem.edu.my/id/eprint/4529/1/NZBHaron_ATS11.pdf http://eprints.utem.edu.my/id/eprint/4529/ |
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| author | Haron, Nor Zaidi Hamdioui, Said |
| author_facet | Haron, Nor Zaidi Hamdioui, Said |
| author_sort | Haron, Nor Zaidi |
| building | UTEM Library |
| collection | Institutional Repository |
| content_provider | Universiti Teknikal Malaysia Melaka |
| content_source | UTEM Institutional Repository |
| continent | Asia |
| country | Malaysia |
| description | Hybrid CMOS/memristor memory (hybrid memory) technology is one of the emerging memory technologies potentially to replace conventional non-volatile flash memory. Existing research on such novel circuits focuses mainly on the integration between CMOS and non-CMOS, fabrication techniques and reliability improvement. However, research
on defect analysis for yield and quality improvement is still in its infancy stage. This paper presents a framework of defect oriented testing in hybrid memory based on electrical simulation. First, a classification and definition of defects is introduced. Second, a simulation model for defect injection and circuit simulation is proposed. Third, a case study to illustrate how the proposed approach can be used to analyze the defects and translate their electrical faulty behavior into fault models - in order to develop the appropriate tests and
design for testability schemes - is provided. The simulation
results show that in addition to the occurrence of conventional semiconductor memories faults, new unique faults take place, e.g., faults that cause the cell to hold an undefined state. These new unique faults require new test approaches (e.g., DfT) in order to be able to detect them. |
| format | Conference or Workshop Item |
| id | my.utem.eprints-4529 |
| institution | Universiti Teknikal Malaysia Melaka |
| language | en |
| publishDate | 2011 |
| record_format | eprints |
| spelling | my.utem.eprints-45292015-05-28T03:25:56Z http://eprints.utem.edu.my/id/eprint/4529/ On Defect Oriented Testing for Hybrid CMOS/memristor Memory Haron, Nor Zaidi Hamdioui, Said TK Electrical engineering. Electronics Nuclear engineering Hybrid CMOS/memristor memory (hybrid memory) technology is one of the emerging memory technologies potentially to replace conventional non-volatile flash memory. Existing research on such novel circuits focuses mainly on the integration between CMOS and non-CMOS, fabrication techniques and reliability improvement. However, research on defect analysis for yield and quality improvement is still in its infancy stage. This paper presents a framework of defect oriented testing in hybrid memory based on electrical simulation. First, a classification and definition of defects is introduced. Second, a simulation model for defect injection and circuit simulation is proposed. Third, a case study to illustrate how the proposed approach can be used to analyze the defects and translate their electrical faulty behavior into fault models - in order to develop the appropriate tests and design for testability schemes - is provided. The simulation results show that in addition to the occurrence of conventional semiconductor memories faults, new unique faults take place, e.g., faults that cause the cell to hold an undefined state. These new unique faults require new test approaches (e.g., DfT) in order to be able to detect them. 2011 Conference or Workshop Item PeerReviewed application/pdf en http://eprints.utem.edu.my/id/eprint/4529/1/NZBHaron_ATS11.pdf Haron, Nor Zaidi and Hamdioui, Said (2011) On Defect Oriented Testing for Hybrid CMOS/memristor Memory. In: 2011 Asian Test Symposium, 20-23 November 2011, New Delhi, India. |
| spellingShingle | TK Electrical engineering. Electronics Nuclear engineering Haron, Nor Zaidi Hamdioui, Said On Defect Oriented Testing for Hybrid CMOS/memristor Memory |
| title | On Defect Oriented Testing for Hybrid CMOS/memristor Memory |
| title_full | On Defect Oriented Testing for Hybrid CMOS/memristor Memory |
| title_fullStr | On Defect Oriented Testing for Hybrid CMOS/memristor Memory |
| title_full_unstemmed | On Defect Oriented Testing for Hybrid CMOS/memristor Memory |
| title_short | On Defect Oriented Testing for Hybrid CMOS/memristor Memory |
| title_sort | on defect oriented testing for hybrid cmos/memristor memory |
| topic | TK Electrical engineering. Electronics Nuclear engineering |
| url | http://eprints.utem.edu.my/id/eprint/4529/1/NZBHaron_ATS11.pdf http://eprints.utem.edu.my/id/eprint/4529/ |
| url_provider | http://eprints.utem.edu.my/ |