Application of Taguchi Method in Optimization of Gate Oxide and Silicide Thickness for 45nm NMOS Device
The optimization of 45nm NMOS device was studied using Taguchi Method. This method was used to analyze the experimental data in order to get the optimum results. In this paper, there are four factors were varied for 3 levels to perform 9 experiments. Silicide on the poly-Si gate electrode was us...
Saved in:
| Main Author: | |
|---|---|
| Format: | Article |
| Language: | en |
| Published: |
IJENS Publishers
2009
|
| Subjects: | |
| Online Access: | http://eprints.utem.edu.my/id/eprint/3792/1/%28J1%29_97010-0404_IJET-IJENS.pdf http://eprints.utem.edu.my/id/eprint/3792/ http://www.ijens.org/index.htm |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| _version_ | 1832715999421399040 |
|---|---|
| author | Fauziyah, Salehuddin |
| author_facet | Fauziyah, Salehuddin |
| author_sort | Fauziyah, Salehuddin |
| building | UTEM Library |
| collection | Institutional Repository |
| content_provider | Universiti Teknikal Malaysia Melaka |
| content_source | UTEM Institutional Repository |
| continent | Asia |
| country | Malaysia |
| description | The optimization of 45nm NMOS device was studied
using Taguchi Method. This method was used to analyze the
experimental data in order to get the optimum results. In this
paper, there are four factors were varied for 3 levels to perform
9 experiments. Silicide on the poly-Si gate electrode was used to
reduce the gate electrode resistance. The virtually fabrication of
45nm NMOS device was performed by using ATHENA module.
While the electrical characterization of device was implemented
by using ATLAS module. The values of oxide and silicide
thickness after optimization approach were 1.52709nm and
25.26nm respectively. The result of the threshold voltage (VTH) is
0.148468 Volts. In this research, silicide thickness and oxide
thickness are the main factors were identified as the source of the
inability of the transistors to perform. The oxide thickness also
was identified as one of the factors that has the strongest effect on
the response characteristics. |
| format | Article |
| id | my.utem.eprints-3792 |
| institution | Universiti Teknikal Malaysia Melaka |
| language | en |
| publishDate | 2009 |
| publisher | IJENS Publishers |
| record_format | eprints |
| spelling | my.utem.eprints-37922021-11-25T12:04:25Z http://eprints.utem.edu.my/id/eprint/3792/ Application of Taguchi Method in Optimization of Gate Oxide and Silicide Thickness for 45nm NMOS Device Fauziyah, Salehuddin TA Engineering (General). Civil engineering (General) The optimization of 45nm NMOS device was studied using Taguchi Method. This method was used to analyze the experimental data in order to get the optimum results. In this paper, there are four factors were varied for 3 levels to perform 9 experiments. Silicide on the poly-Si gate electrode was used to reduce the gate electrode resistance. The virtually fabrication of 45nm NMOS device was performed by using ATHENA module. While the electrical characterization of device was implemented by using ATLAS module. The values of oxide and silicide thickness after optimization approach were 1.52709nm and 25.26nm respectively. The result of the threshold voltage (VTH) is 0.148468 Volts. In this research, silicide thickness and oxide thickness are the main factors were identified as the source of the inability of the transistors to perform. The oxide thickness also was identified as one of the factors that has the strongest effect on the response characteristics. IJENS Publishers 2009-12-10 Article PeerReviewed text en http://eprints.utem.edu.my/id/eprint/3792/1/%28J1%29_97010-0404_IJET-IJENS.pdf Fauziyah, Salehuddin (2009) Application of Taguchi Method in Optimization of Gate Oxide and Silicide Thickness for 45nm NMOS Device. International Journal of Engineering & Technology, 9 (10). pp. 94-98. ISSN 2077-1185 (Online) 2227-2712 (Print) http://www.ijens.org/index.htm |
| spellingShingle | TA Engineering (General). Civil engineering (General) Fauziyah, Salehuddin Application of Taguchi Method in Optimization of Gate Oxide and Silicide Thickness for 45nm NMOS Device |
| title | Application of Taguchi Method in Optimization
of Gate Oxide and Silicide Thickness for
45nm NMOS Device |
| title_full | Application of Taguchi Method in Optimization
of Gate Oxide and Silicide Thickness for
45nm NMOS Device |
| title_fullStr | Application of Taguchi Method in Optimization
of Gate Oxide and Silicide Thickness for
45nm NMOS Device |
| title_full_unstemmed | Application of Taguchi Method in Optimization
of Gate Oxide and Silicide Thickness for
45nm NMOS Device |
| title_short | Application of Taguchi Method in Optimization
of Gate Oxide and Silicide Thickness for
45nm NMOS Device |
| title_sort | application of taguchi method in optimization
of gate oxide and silicide thickness for
45nm nmos device |
| topic | TA Engineering (General). Civil engineering (General) |
| url | http://eprints.utem.edu.my/id/eprint/3792/1/%28J1%29_97010-0404_IJET-IJENS.pdf http://eprints.utem.edu.my/id/eprint/3792/ http://www.ijens.org/index.htm |
| url_provider | http://eprints.utem.edu.my/ |