Optimization and analysis of FPGA-based systolic array for matrix multiplication

Optimization and analysis of FPGA-based systolic array for matrix multiplication

Over the years, field-programmable gate array (FPGA)-based accelerators have attracted interest and attention due to their performance and energy efficiency factors. This paper presents an optimized FPGA-based accelerator using a systolic array for matrix multiplication. In a systolic array, many id...

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Bibliographic Details
Main Authors: Shapri, Ahmad Husni Mohd, Rahman, Norazeani Abdul, Zakaria, Syed Muhammad Mamduh Syed, Chieh, Kiu Kwong, Saat, Shakir
Format: Conference or Workshop Item
Language:en
Published: 2024
Online Access:http://eprints.utem.edu.my/id/eprint/28813/1/Optimization%20and%20analysis%20of%20FPGA-based%20systolic%20array%20for%20matrix%20multiplication.pdf
http://eprints.utem.edu.my/id/eprint/28813/
https://doi.org/10.1063/5.0192098
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http://eprints.utem.edu.my/id/eprint/28813/1/Optimization%20and%20analysis%20of%20FPGA-based%20systolic%20array%20for%20matrix%20multiplication.pdf
http://eprints.utem.edu.my/id/eprint/28813/
https://doi.org/10.1063/5.0192098

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