Virtual fabrication in modelling 14 nm horizontal double gate bilayer graphene FET NMOS/PMOS - Mohd Nizam, Nur Hazwani Naili; Abdul Hamid, Afifah Maheran; Salehuddin, Fauziyah; K. E., Kaharudin; Z. A., Noor Faizah (2024)
MOSFET has been the most widely utilized electronic appliance in integrated circuits (ICs) since the beginning of the silicon-based semiconductor material (1970s). With the rapid development of the semiconductor industry, the feature size of MOSFETs has been drastically reduced. In this paper, the modeling 14 nm NMOS and PMOS horizontal double gate with deposit bilayer graphene, high-κ dielectric, and the metal gate is presented by using the Athena module while the characterization of the device is presented by using the Atlas module. It demonstrates that the virtual fabrication using Athena was successfully designed by using HfO2 and WSix as high-κ dielectric and metal gates, respectively, for NMOS transistors, and HfO2 and TiSix for PMOS transistors. The simulation shows that the VTH value of the 14 nm channel length is within 12.7% of 0.191 V and the IOFF value is lower than 100 nA/μm. The values of the VTH NMOS and PMOS were 0.20473 and 0.19154, respectively. In the meantime, the IOFF values for PMOS and NMOS devices were 45.0861 nA/μm and 4.59273 nA/μm, respectively. It proves that the value of the VTH and IOFF is in line with ITRS 2013 for high-performance applications. These findings are expected to serve as a benchmark for future efforts to fabricate 14 nm devices using bilayer graphene/high-κ dielectric/metal gate MOSFETs with gate lengths of 14 nm.