A lightweight authentication scheme using physical unclonable function for FPGA-based IoT applications - Ishak, Mohammad Haziq (2024)
The Internet of Things (IoT) describes the network of physical devices equipped with sen-sors and other technologies. This interconnectivity facilitates data exchange for process-ing and analysis, demanding a high level of trust to ensure security and authenticity for resource-constrained IoT devices. Physical Unclonable Functions (PUFs) have emerged as a promising solution to establish the root of trust for lightweight IoT devices. PUFs ex-ploit the random intrinsic manufacturing process variations, creating unique and random mappings of challenge-response pairs (CRPs) specific to each PUF instance. This charac-teristic makes PUFs a promising technology for robust security applications. However, the PUF-based authentication scheme based on the CRPs database requires storing CRPs in the verifier database, which becomes a challenge as the number of devices to be authenticated grows. Additionally, while PUFs are physically unclonable, their function is susceptible to modelling attacks from machine learning (ML) techniques. Thus, developing secure PUFs for lightweight applications presents a significant challenge. Therefore, this thesis presents a lightweight authentication scheme without a CRP database by constructing a model of Arbiter-PUF with a challenge permutation technique in the verifier. This thesis presents three significant contributions. The first contribution presents the implementation of a phys-ical Arbiter-PUF with random challenge permutation on Xilinx Artix-7 Field Programmable Gate Array (FPGA) boards. The relative placement method is used to ensure the symmet-ric routing for the physical Arbiter-PUF. As a result, the physical Arbiter- PUF achieves good quality in PUF metrics with 52.5% uniqueness, 96.87% steadiness, and 47.5% uni-formity. In addition, the implementation of the random challenge permutation technique has successfully reduced ML-Attack vulnerability to ≈59% with 20,000 CRPs. The second contribution for this thesis is the implementation of the Arbiter-PUF model using the Arti-ficial Neural Network (ANN) technique with random challenge permutation in the Xilinx Artix-7 FPGA board. The model is trained using MATLAB application with extracted CRPs from the physical Arbiter-PUF, achieving an accuracy of ≈98%. The successfully trained Arbiter-PUF model is subsequently designed in Xilinx System Generator and converted into an intellectual property (IP) core, which is then programmed into FPGA boards. Finally, the third contribution is the development of a lightweight PUF-based authentication scheme be-tween the verifier (Arbiter-PUF model) and prover (physical Arbiter-PUF). The lightweight authentication scheme is implemented on two Xilinx Artix-7 FPGA boards, which serve as a verifier and a prover. Based on the validation of the authentication scheme, the verifier manages to differentiate between the genuine and the fake prover. Furthermore, the authenti-cation scheme consumes 6.67× less area compared to the PUF-based authentication scheme based on the CRPs database for 1000 authentication processes and the power consumption for overall system’s power demands consumes only 67mW, indicating a relatively low power requirement, making it well-suited for resource-constrained IoT applications.