APA (7th ed.) Citation

Ikiri, Y., Yotsuyanagi, H., Ali, F. A., Lu, S., & Hashizume, M. (2023). A DFT technique for electrical interconnect testing of circuit boards with 3D Stacked SRAM ICs.

Chicago Style (17th ed.) Citation

Ikiri, Yuki, Hiroyuki Yotsuyanagi, Fara Ashikin Ali, Shyue-Kung Lu, and Masaki Hashizume. A DFT Technique for Electrical Interconnect Testing of Circuit Boards with 3D Stacked SRAM ICs. 2023.

MLA (9th ed.) Citation

Ikiri, Yuki, et al. A DFT Technique for Electrical Interconnect Testing of Circuit Boards with 3D Stacked SRAM ICs. 2023.