On-Chip Power Management System Based CMOS Reconfigurable Switched Capacitor DC-DC Converter For Battery-Less Iot Soc - Mohd Kamel, Mohamad Khairul (2019)
In recent studies, Radio Frequency (RF) energy harvesting method showed a great potential for indefinite battery lifetime for Internet of Things (IoT) System on Chip (SoC) application which is a system with functional blocks that includes sensors, memory, processing, and data transmission unit. However, the harvested energy is not stable and could not supply enough energy as required by each functional block of IoT SoC. Thus, it needs to be regulated and reconfigured to different levels of Direct Current (DC) supplies. Switched Capacitor (SC) DC-DC converter can be used for this purpose since it can regulate the energy to a stable level by stepping it up or down. But this conventional design has a drawback in fix conversion ratio, thus limited only to either step-up or step-down mode at one time and not simultaneously. Another drawback is SC DC-DC converter is only suitable for low load current application which is only in µA range, thus it requires a Low Dropout (LDO) voltage regulator added as an additional block to fulfil the requirement for high load current in microampere (mA) range. Hence, this work presents the design of a reconfigurable on-chip power management system based on CMOS SC DC-DC converter that can operate in both step-up and step-down simultaneously for battery-less IoT SoC. A method to achieve reconfigurability is proposed based on switching frequency parameter that is generated by Current-Starved Voltage-Controlled Oscillator (CSVCRO). Based on the simulation result, the CSVCRO enables the SC DC-DC converter to operate in both step-up and step-down modes for an input voltage range of 0.9V to 1.5V. The LDO design consists of error amplifier, bandgap voltage reference, feedback network resistor and series-pass transistor. NMOS transistor has been proposed to replace conventional Bipolar Junction Transistor (BJT) in bandgap voltage circuit to overcome the error amplifier input transistor driving voltage problem. In the simulation, the LDO performance has achieved 90.85dB of open-loop gain, 76.39º of phase margin and 63.46dB of Power Supply Ripple Rejection (PSRR) respectively. The simulations had also been validated through fabrication, measurement analysis, and benchmarking with existing works. Furthermore, it can be seen that the stability of the proposed design is higher compared to the previous research work which is at 75º. It is hopeful that the contribution from this work can be used to achieve more advancement in power management unit development based on CMOS technology and be the future of the microelectronic field.