An Experimental Study Of Combinational Logic Circuit Minimization Using Firefly Algorithm - Zainodin, Aznilinda; Ab. Kadir, Aida Khairunnisaa; Ayob, M Nasir; Hassan, Ahmad Fariz; Zainal Abidin, Amar Faiz; Zahid, Fazlinashatul Suhaidah; Jaafar, Hazriq Izzuan; Mohd Khairuddin, Ismail (2014)

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Combinatorial logic circuit minimization is usually done using Karnaugh’s Map or Boolean equation. This paper presents an application of Firefly Algorithm to design combinational logic circuit in which the objective function is to minimize the total number of gates used. Then, the algorithm is benchmarked with other literatures. Result indicates that it able to find optimal solution but further analysis is required for a more complex combinatorial logic circuit minimization.