The Design Of High-Speed Cmos Pipelined Adc And Hybrid Dac For Wireless Communication
The increasing data rates required by cutting-edge wireless communication systems have intensified the demand for high-speed adcs and dacs. Therefore, this research presents an innovative 16-bit 400 ms/s pipelined adc and hybrid dac, designed using the 65 nm cmos process and a supply voltage of 1 v....
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| Format: | Thesis |
| Language: | en |
| Published: |
2024
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| Subjects: | |
| Online Access: | http://eprints.usm.my/63589/1/24%20Pages%20from%20NORHAMIZAH%20BINTI%20IDROS.pdf http://eprints.usm.my/63589/ |
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| Summary: | The increasing data rates required by cutting-edge wireless communication systems have intensified the demand for high-speed adcs and dacs. Therefore, this research presents an innovative 16-bit 400 ms/s pipelined adc and hybrid dac, designed using the 65 nm cmos process and a supply voltage of 1 v. In pipelined adcs, resolution and sampling rate are primarily constrained by open-loop dc gain and unity-gain frequency of operational amplifier (op-amp) as their core component. However, achieving high-performance op-amp comes at the cost of increased power consumption. Therefore, the proposed adc features an inventive dual gain boosting op-amp that surpasses a unity-gain frequency of 5 ghz and an open-loop dc gain of 100 db. The adc occupies an active area of 0.83 mm² and consumes 50 mw of power. The adc exhibits an sndr of 73.0 db, resulting in a schreier fom of 168 db. The high-speed systems also introduces glitches in dacs, which severely impair the linearity and overall dac performance. Glitch-reduction techniques enhance the performance of dacs, with the trade-off in power consumption. Hence, this research proposes a novel hybrid dac, incorporates a digital filtering mechanism designed to eliminate glitches. The dac combines a 6-msb current-steering and a 10-lsb binary-weighted resistor architectures, resulting a total power consumption of 8.36 mw within an active area of 0.06 mm². |
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