Effect Of The Number Of Tapping Bits Of The A5/1 Stream Cipher Towards Hardware Performance
A5/1 stream cipher is a type of cryptographic algorithm which is widely used for encryption of the GSM communication. While numerous work on the modification of the conventional design of the A5/1 stream have been carried out, to the best of author’s knowledge, they are mainly tested in terms of th...
Saved in:
| Main Authors: | , , , |
|---|---|
| Format: | Article |
| Language: | en |
| Published: |
AENSI Publisher
2024
|
| Subjects: | |
| Online Access: | http://www.sci-int.com/pdf/636300137955519831.pdf |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| Summary: | A5/1 stream cipher is a type of cryptographic algorithm which is widely used for encryption of the GSM
communication. While numerous work on the modification of the conventional design of the A5/1 stream have been carried out, to the best of author’s knowledge, they are mainly tested in terms of the randomness (and hence security) level, whereas the practicality of the algorithm’s design in hardware is typically overlooked. Objective: In this paper, two modified designs proposed by the author are implemented into hardware and the resulting rate of power consumption is compared with that of the conventional design of the A5/1 stream cipher. Results: The results obtained shows that the rate of power consumption of the hardware is inversely proportional to that of the number of tapping bits used in the design. Conclusion: While the tapping
bits are known to play a minor role when it comes to generating random binary sequence (and following it, the strength of the security of the design), it actually plays a positive role when it comes to increasing the efficiency of the performance of the hardware.
Keywords: A5/1 stream cipher, FPGA, hardware performance |
|---|