Optimization of process parameter variation in 45nm p-channel MOSFET using L18 orthogonal array
In this study, orthogonal array of L18 in Taguchi method was used to optimize the process parameters variance on threshold voltage (V TH) in 45nm p-channel Metal Oxide Semiconductor Field Effect Transistor (MOSFET) device. The signal-to-noise (S/N) ratio and analysis of variance (ANOVA) are employed...
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2023
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| author | Salehuddin F. Ahmad I. Hamid F.A. Zaharim A. Hamid A.M.A. Menon P.S. Elgomati H.A. Majlis B.Y. Apte P.R. |
| author2 | 36239165300 |
| author_facet | 36239165300 Salehuddin F. Ahmad I. Hamid F.A. Zaharim A. Hamid A.M.A. Menon P.S. Elgomati H.A. Majlis B.Y. Apte P.R. |
| author_sort | Salehuddin F. |
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| content_provider | Universiti Tenaga Nasional |
| content_source | UNITEN Institutional Repository |
| continent | Asia |
| country | Malaysia |
| description | In this study, orthogonal array of L18 in Taguchi method was used to optimize the process parameters variance on threshold voltage (V TH) in 45nm p-channel Metal Oxide Semiconductor Field Effect Transistor (MOSFET) device. The signal-to-noise (S/N) ratio and analysis of variance (ANOVA) are employed to study the performance characteristics of the PMOS device. There are eight process parameters (control factors) were varied for 2 and 3 levels to performed 18 experiments. Whereas, the two noise factors were varied for 2 levels to get four readings of VTH for every row of experiment. VTH results were used as the evaluation variable. This work was done using TCAD simulator, consisting of a process simulator, ATHENA and device simulator, ATLAS. These two simulators were combined with L 18 Orthogonal Array to aid in design and optimize the process parameters. The predicted values of the process parameters were verified successfully with ATHENA and ATLAS's simulator. In PMOS device, VTH implant dose (26%) and compensate implant dose (26%) were the major factors affecting the threshold voltage. While S/D Implant was identified as an adjustment factor in PMOS device. These adjustment factors have been used to get the nominal values of threshold voltage for PMOS device closer to -0.289V. � 2012 IEEE. |
| format | Conference paper |
| id | my.uniten.dspace-29491 |
| institution | Universiti Tenaga Nasional |
| publishDate | 2023 |
| record_format | dspace |
| spelling | my.uniten.dspace-294912023-12-28T14:30:15Z Optimization of process parameter variation in 45nm p-channel MOSFET using L18 orthogonal array Salehuddin F. Ahmad I. Hamid F.A. Zaharim A. Hamid A.M.A. Menon P.S. Elgomati H.A. Majlis B.Y. Apte P.R. 36239165300 12792216600 6603573875 15119466900 36570222300 57201289731 36536722700 6603071546 55725529100 Leakage Current NMOS Device Taguchi Method Threshold Voltage Electron beam lithography Experiments Leakage currents Optimization Simulators Taguchi methods Threshold voltage 3 levels Adjustment factors Control factors Device simulators Major factors MOS-FET NMOS devices Noise factor Nominal values Optimization of process parameters Orthogonal array P channels Performance characteristics pMOS devices Process parameters Process simulators Signal to noise (S/N) ratios MOSFET devices In this study, orthogonal array of L18 in Taguchi method was used to optimize the process parameters variance on threshold voltage (V TH) in 45nm p-channel Metal Oxide Semiconductor Field Effect Transistor (MOSFET) device. The signal-to-noise (S/N) ratio and analysis of variance (ANOVA) are employed to study the performance characteristics of the PMOS device. There are eight process parameters (control factors) were varied for 2 and 3 levels to performed 18 experiments. Whereas, the two noise factors were varied for 2 levels to get four readings of VTH for every row of experiment. VTH results were used as the evaluation variable. This work was done using TCAD simulator, consisting of a process simulator, ATHENA and device simulator, ATLAS. These two simulators were combined with L 18 Orthogonal Array to aid in design and optimize the process parameters. The predicted values of the process parameters were verified successfully with ATHENA and ATLAS's simulator. In PMOS device, VTH implant dose (26%) and compensate implant dose (26%) were the major factors affecting the threshold voltage. While S/D Implant was identified as an adjustment factor in PMOS device. These adjustment factors have been used to get the nominal values of threshold voltage for PMOS device closer to -0.289V. � 2012 IEEE. Final 2023-12-28T06:30:14Z 2023-12-28T06:30:14Z 2012 Conference paper 10.1109/SMElec.2012.6417127 2-s2.0-84874123696 https://www.scopus.com/inward/record.uri?eid=2-s2.0-84874123696&doi=10.1109%2fSMElec.2012.6417127&partnerID=40&md5=f87fd96bcb96b278466f3e1adad88e5b https://irepository.uniten.edu.my/handle/123456789/29491 6417127 219 223 Scopus |
| spellingShingle | Leakage Current NMOS Device Taguchi Method Threshold Voltage Electron beam lithography Experiments Leakage currents Optimization Simulators Taguchi methods Threshold voltage 3 levels Adjustment factors Control factors Device simulators Major factors MOS-FET NMOS devices Noise factor Nominal values Optimization of process parameters Orthogonal array P channels Performance characteristics pMOS devices Process parameters Process simulators Signal to noise (S/N) ratios MOSFET devices Salehuddin F. Ahmad I. Hamid F.A. Zaharim A. Hamid A.M.A. Menon P.S. Elgomati H.A. Majlis B.Y. Apte P.R. Optimization of process parameter variation in 45nm p-channel MOSFET using L18 orthogonal array |
| title | Optimization of process parameter variation in 45nm p-channel MOSFET using L18 orthogonal array |
| title_full | Optimization of process parameter variation in 45nm p-channel MOSFET using L18 orthogonal array |
| title_fullStr | Optimization of process parameter variation in 45nm p-channel MOSFET using L18 orthogonal array |
| title_full_unstemmed | Optimization of process parameter variation in 45nm p-channel MOSFET using L18 orthogonal array |
| title_short | Optimization of process parameter variation in 45nm p-channel MOSFET using L18 orthogonal array |
| title_sort | optimization of process parameter variation in 45nm p-channel mosfet using l18 orthogonal array |
| topic | Leakage Current NMOS Device Taguchi Method Threshold Voltage Electron beam lithography Experiments Leakage currents Optimization Simulators Taguchi methods Threshold voltage 3 levels Adjustment factors Control factors Device simulators Major factors MOS-FET NMOS devices Noise factor Nominal values Optimization of process parameters Orthogonal array P channels Performance characteristics pMOS devices Process parameters Process simulators Signal to noise (S/N) ratios MOSFET devices |
| url_provider | http://dspace.uniten.edu.my/ |