Designing and optimizing digital circuit using FPSGA and DH
This paper is presents the analysis of designing and optimizing digital circuit structure using Finite Persisting Sphere Genetic Algorithm (FPSGA) and (Double Helix) DH representation. The design is involved 4 Input and 1 Output of digital circuit with 6 min terms. The resulted circuit is verified u...
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| Format: | Conference paper |
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2023
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| _version_ | 1833409852907454464 |
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| author | Kamil K. Chong K.H. Raveendran S.K. |
| author2 | 57195622807 |
| author_facet | 57195622807 Kamil K. Chong K.H. Raveendran S.K. |
| author_sort | Kamil K. |
| building | UNITEN Library |
| collection | Institutional Repository |
| content_provider | Universiti Tenaga Nasional |
| content_source | UNITEN Institutional Repository |
| continent | Asia |
| country | Malaysia |
| description | This paper is presents the analysis of designing and optimizing digital circuit structure using Finite Persisting Sphere Genetic Algorithm (FPSGA) and (Double Helix) DH representation. The design is involved 4 Input and 1 Output of digital circuit with 6 min terms. The resulted circuit is verified using XILINX ISE Design Suite 13.2. The result obtained shows that the circuit is function and able to operate with minimum number of gates. � 2013 IEEE. |
| format | Conference paper |
| id | my.uniten.dspace-29383 |
| institution | Universiti Tenaga Nasional |
| publishDate | 2023 |
| record_format | dspace |
| spelling | my.uniten.dspace-293832023-12-28T12:12:49Z Designing and optimizing digital circuit using FPSGA and DH Kamil K. Chong K.H. Raveendran S.K. 57195622807 36994481200 57064141200 Engineering Industrial engineering Circuit structures Double helix Number of gates Optimization This paper is presents the analysis of designing and optimizing digital circuit structure using Finite Persisting Sphere Genetic Algorithm (FPSGA) and (Double Helix) DH representation. The design is involved 4 Input and 1 Output of digital circuit with 6 min terms. The resulted circuit is verified using XILINX ISE Design Suite 13.2. The result obtained shows that the circuit is function and able to operate with minimum number of gates. � 2013 IEEE. Final 2023-12-28T04:12:49Z 2023-12-28T04:12:49Z 2013 Conference paper 10.1109/PEOCO.2013.6564536 2-s2.0-84882767954 https://www.scopus.com/inward/record.uri?eid=2-s2.0-84882767954&doi=10.1109%2fPEOCO.2013.6564536&partnerID=40&md5=73eeb53f7826e64909639b80ac567b04 https://irepository.uniten.edu.my/handle/123456789/29383 6564536 167 171 Scopus |
| spellingShingle | Engineering Industrial engineering Circuit structures Double helix Number of gates Optimization Kamil K. Chong K.H. Raveendran S.K. Designing and optimizing digital circuit using FPSGA and DH |
| title | Designing and optimizing digital circuit using FPSGA and DH |
| title_full | Designing and optimizing digital circuit using FPSGA and DH |
| title_fullStr | Designing and optimizing digital circuit using FPSGA and DH |
| title_full_unstemmed | Designing and optimizing digital circuit using FPSGA and DH |
| title_short | Designing and optimizing digital circuit using FPSGA and DH |
| title_sort | designing and optimizing digital circuit using fpsga and dh |
| topic | Engineering Industrial engineering Circuit structures Double helix Number of gates Optimization |
| url_provider | http://dspace.uniten.edu.my/ |