Optimisation of process parameters for lower leakage current in 22 nm n-type MOSFET device using Taguchi method
In this article, Taguchi orthogonal array method was used to optimize the process parameters during the design of a 22 nm n-type Metal Oxide Semiconductor Field Effect Transistor (MOSFET) in order to decrease the leakage current (ILEAK) of the device. Titanium dioxide (TiO2) was used as the dielectr...
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Penerbit UTM Press
2023
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| author | Afifah Maheran A.H. Menon P.S. Ahmad I. Shaari S. |
| author2 | 36570222300 |
| author_facet | 36570222300 Afifah Maheran A.H. Menon P.S. Ahmad I. Shaari S. |
| author_sort | Afifah Maheran A.H. |
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| content_provider | Universiti Tenaga Nasional |
| content_source | UNITEN Institutional Repository |
| continent | Asia |
| country | Malaysia |
| description | In this article, Taguchi orthogonal array method was used to optimize the process parameters during the design of a 22 nm n-type Metal Oxide Semiconductor Field Effect Transistor (MOSFET) in order to decrease the leakage current (ILEAK) of the device. Titanium dioxide (TiO2) was used as the dielectric layer to replace the traditional silicon dioxide SiO2 and tungsten silicide (WSix) was used as a metal gate to replace polysilicon. The device's fabrication and electrical characterization were executed using ATHENA and ATLAS modules from Silvaco International. Taguchi's Power of Three Series L9 orthogonal array was used to optimize the device process parameters and to finally predict the best process parameter combination to obtain the minimum leakage current (ILEAK) using Smaller-the-Better (STB) signal-to-noise ratio (SNR). The optimization resulted in the attainment of the lowest ILEAK mean value of 0.25759 nA/?m which is in accordance to the predicted value given in the International Technology Roadmap for Semiconductors (ITRS) 2011. © 2014 Penerbit UTM Press. All rights reserved. |
| format | Conference Paper |
| id | my.uniten.dspace-22041 |
| institution | Universiti Tenaga Nasional |
| publishDate | 2023 |
| publisher | Penerbit UTM Press |
| record_format | dspace |
| spelling | my.uniten.dspace-220412023-05-16T10:46:53Z Optimisation of process parameters for lower leakage current in 22 nm n-type MOSFET device using Taguchi method Afifah Maheran A.H. Menon P.S. Ahmad I. Shaari S. 36570222300 57201289731 12792216600 6603595092 In this article, Taguchi orthogonal array method was used to optimize the process parameters during the design of a 22 nm n-type Metal Oxide Semiconductor Field Effect Transistor (MOSFET) in order to decrease the leakage current (ILEAK) of the device. Titanium dioxide (TiO2) was used as the dielectric layer to replace the traditional silicon dioxide SiO2 and tungsten silicide (WSix) was used as a metal gate to replace polysilicon. The device's fabrication and electrical characterization were executed using ATHENA and ATLAS modules from Silvaco International. Taguchi's Power of Three Series L9 orthogonal array was used to optimize the device process parameters and to finally predict the best process parameter combination to obtain the minimum leakage current (ILEAK) using Smaller-the-Better (STB) signal-to-noise ratio (SNR). The optimization resulted in the attainment of the lowest ILEAK mean value of 0.25759 nA/?m which is in accordance to the predicted value given in the International Technology Roadmap for Semiconductors (ITRS) 2011. © 2014 Penerbit UTM Press. All rights reserved. Final 2023-05-16T02:46:53Z 2023-05-16T02:46:53Z 2014 Conference Paper 10.11113/jt.v68.2987 2-s2.0-84906853095 https://www.scopus.com/inward/record.uri?eid=2-s2.0-84906853095&doi=10.11113%2fjt.v68.2987&partnerID=40&md5=ee08aee0ec86af8ca347f0331b3d388b https://irepository.uniten.edu.my/handle/123456789/22041 68 4 1 5 Penerbit UTM Press Scopus |
| spellingShingle | Afifah Maheran A.H. Menon P.S. Ahmad I. Shaari S. Optimisation of process parameters for lower leakage current in 22 nm n-type MOSFET device using Taguchi method |
| title | Optimisation of process parameters for lower leakage current in 22 nm n-type MOSFET device using Taguchi method |
| title_full | Optimisation of process parameters for lower leakage current in 22 nm n-type MOSFET device using Taguchi method |
| title_fullStr | Optimisation of process parameters for lower leakage current in 22 nm n-type MOSFET device using Taguchi method |
| title_full_unstemmed | Optimisation of process parameters for lower leakage current in 22 nm n-type MOSFET device using Taguchi method |
| title_short | Optimisation of process parameters for lower leakage current in 22 nm n-type MOSFET device using Taguchi method |
| title_sort | optimisation of process parameters for lower leakage current in 22 nm n-type mosfet device using taguchi method |
| url_provider | http://dspace.uniten.edu.my/ |