Exploring distance-based wireless transceiver placements for wireless network-on-chip architecture with deterministic routing algorithms - Asrani, Lit; Shamsiah, Suhaili; Kuryati, Kipli; Rohana, Sapawi; Fariza, Mahyan (Institute of Advanced Engineering and Science (IAES), 2025)
Network-on-chip (NoC) technology is crucial for integrating multiple embedded computing cores onto a single chip. Consequently, this has led to the development of the wireless network-on-chip (WiNoC) concept, seen as a promising strategy to overcome scalability issues in communication systems within chips for future many-core architectures. This research analyses the impact of wireless transceiver subnet clustering on the hundred-core mesh-structured WiNoC architecture. The study aims to examine the effects of distance-based wireless transceiver placements on the transmission delay, network throughput, and energy consumption within a mesh wireless NoC architecture featuring a hundred cores, under specific routing strategies: X-Y, west-first, negative-first, and north-last. This research investigates the impact of positioning radio subnets at the farthest, farther, nearest, and closest positions within an architecture equipped with four wireless transceivers. The Noxim simulator was utilised to simulate the analysed wireless transceiver placements within the hundred-core mesh-structured WiNoC designs, with the objective of validating the results. The architecture with the wireless transceivers positioned at midway proximity (nearer and further) demonstrated the best performance, as evidenced by the lowest latencies for all evaluated deterministic routing algorithms, according to the simulation outcomes.