Performance and energy evaluation of dynamic adaptive deterministic routing algorithm for multicore architectures - Asrani, Lit; Maimun, Huja Hussin; Shamsiah, Suhaili (Elsevier Ltd., 2024)
Chip Multiprocessors (CMPs) leverage multiple processing units to improve computational speed and efficiency. Routing algorithms in NoC (Network-on-Chip) architectures ensure efficient data communication between these units, addressing challenges such as congestion, latency, and power consumption. This paper delves into an extensive analysis of the performance evaluation concerning the Dynamic Adaptive Deterministic (DyAD) routing for Network-on-Chip (NoC) and Wireless Network-on-Chip (WiNoC) configurations within the framework of a 64-core and 100-core multicore architecture. The evaluation involved a congestion threshold analysis of data transmission latency, the efficiency of network data throughput, and the amount of energy consumed. To substantiate our conclusions, we conducted simulations of the 64-core and 100-core mesh-based NoC and WiNoC architectures under the Video Image Processing System (VIPS) benchmark workload. These simulations were executed utilizing the Noxim simulator, a well-recognized tool acclaimed for its capacity to provide cycleaccurate simulations. Analyzing the simulation outcomes, it becomes evident that the DyAD routing approach for the 64-core and 100-core WiNoC architecture performs better in terms of network performance. It is characterized by enhanced capabilities at higher Packet Injection Rate (PIR) saturation loads, improved network throughput, and minimized latencies. This dominance is evident from its ability to handle heavier workloads and achieve lower delays in the investigated VIPS workload situations, compared to the 64-core and 100-core NoC multicore architecture.