Delay Aware Topology Generation for Network on Chip

Network-on-Chip (NoC) is a scalable bandwidth requirement that using on-chip packet-switched micro-network of interconnects. NoC are based on System-on-Chips(SoCs) that traditionally large-scale multi-processors and distributed computing networks. The NoC performances analysis were evaluated in term...

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Bibliographic Details

Main Authors:	Asrani, Lit, Fariza, Mahyan, Termimi Hidayat, Mahyan
Format:	Book
Language:	en
Published:	LAP LAMBERT Academic Publishing 2015
Subjects:	QA75 Electronic computers. Computer science
Online Access:	http://ir.unimas.my/id/eprint/41659/1/Delay%20Aware%20Topology.pdf http://ir.unimas.my/id/eprint/41659/
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