Area Optimization for Networks-on-Chip Architectures using Deep Network Partitioning

This paper presents an area optimization for Network-on-Chip (NoC) architecture using deep Network Par- titioning technique. Among the hardest problems in NoC design is customizing the topological structure and application mapping on on-chip network in order to cater for application demand at minima...

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Bibliographic Details

Main Authors:	Asrani, Lit, Hazrul, Mohamed Basri, M. N., Marsono, S. N. S., Hussin, Yee, O. C.
Format:	Proceeding
Language:	en
Published:	2011
Subjects:	TK Electrical engineering. Electronics Nuclear engineering
Online Access:	http://ir.unimas.my/id/eprint/41637/3/Area%20Optimization.pdf http://ir.unimas.my/id/eprint/41637/
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