Power Optimization for Mesh Network-on-Chip Architecture: Multilevel Network Partitioning Approach
This paper presents a power optimization for mesh Network-on-Chip (NoC) architecture by using Multilevel Network Partitioning approach. Power consumption is reduced by re-dividing the large networks into few smaller partitions. This approach assigns excessively communicated Intellectual Property (IP...
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| Main Authors: | , , , , , , |
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| Format: | Proceeding |
| Language: | en |
| Published: |
2013
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| Subjects: | |
| Online Access: | http://ir.unimas.my/id/eprint/41635/1/Power_Optimization_for_Mesh_Network_on_C.pdf http://ir.unimas.my/id/eprint/41635/ |
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| Summary: | This paper presents a power optimization for mesh Network-on-Chip (NoC) architecture by using Multilevel Network Partitioning approach. Power consumption is reduced by re-dividing the large networks into few smaller partitions. This approach assigns excessively communicated Intellectual Property (IP) cores into the same portion that result the minimal average inter-core distance. The efficiency of this methodology is verified through a System-on-Chip (SoC) application known as Video Object Plan Decoder (VOPD). Experimental results show a promising improvement of 16.59% in the power consumption. |
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