APA (7th ed.) Citation

Shamsiah, S., Kayle Jacqueline, K., Norhuzaimin, J., Maimun, H. H., Mohd Faizrizwan, M. S., & Asrani, L. (2020). Implementation of Verilog HDL in Calculator Design with FPGA Simulation. IEEE.

Chicago Style (17th ed.) Citation

Shamsiah, Suhaili, Kumar Kayle Jacqueline, Julai Norhuzaimin, Huja Husin Maimun, Mohd Sabri Mohd Faizrizwan, and Lit Asrani. Implementation of Verilog HDL in Calculator Design with FPGA Simulation. IEEE, 2020.

MLA (9th ed.) Citation

Shamsiah, Suhaili, et al. Implementation of Verilog HDL in Calculator Design with FPGA Simulation. IEEE, 2020.