Design of subsystems for multiband wireless transceiver - Arjuna, Marzuki (Universiti Malaysia Perlis, 2011)
This thesis deals with the development of subsystems for wireless application. The subsystems are Low Noise Amplifier (LNA), Medium Power Amplifier (MPA), Demodulator, Variable Signal Generator (VSG) and Voltage for Current Source (VCS). Several issues such as suitable multiband design flow, robust voltage source for current source, multiband local oscillator for I/Q mixer and high speed switch must be solved. A new design methodology of integrated circuits for multiband application is presented. The design methodology is modified from a typical Monolithic Microwave Integrated Circuit (MMIC) flow. Core based design, parasitic aware approach and power constrained optimization are introduced into the new design flow. Three subsystems circuits of a typical wireless transceiver are designed using the proposed new design flow and described in this thesis. The circuits are LNA, MPA and broadband amplifier. The same core circuit topology is used as main block to design 2.4 GHz and 3.5 GHz LNA and MPA. A power constrained optimization is applied to a test case amplifier i.e. broadband amplifier to get the optimized RF performance. The optimization is simulation-based technique. A 0.15 9m 85 GHz PHEMT is used in designing the LNA, MPA and broadband amplifier. The research on the demodulator is targeted for multiband application and low current consumption. The demodulator was designed for Wideband Code Division Multiple Access (W-CDMA) communication system. Tied collectors at the last two MSDFFs is employed to ease the multiband option. The design of demodulator contained 2 mixers, a local oscillator (LO) divider, negative resistance circuit, buffer amplifiers and bias/control circuits. The Voltage for Current Source is designed using Proportional to Absolute Temperature (PTAT) and Complementary to Absolute Temperature (CTAT) sources with combination of transistors and resistors. The VCS is used to provide voltage for current sources of RFIC blocks in the demodulator. A 0.35 µm SiGe BiCMOS technology with T f = 45 GHz, max f = 60 GHz and Noise Figure = 0.8 dB at 2 GHz was used for the design of demodulator and VCS. A variable signal generator that is capable of fast switching between different center frequencies is designed. The switching time is 4 ns and the three center frequencies at the lower band (UWB bands) are selected, which are 3.35 GHz, 3.85 GHz and 4.35 GHz. The structure of the variable signal generator is based on the topology of active oscillators. By using a switching network, the different frequencies from different cross-coupled LC oscillators are switched within 4 ns. In this design, a new topology of NMOS switch based on series-shunt configuration is proposed so that it is able to pass the signal from oscillators to output without transition spike and free of charge injection problem. A 0.18 µm CMOS technology is used to design the VSG. The MPA core circuit measurement result has at least 0.5 dB differences in power gain compared to parasitic aware simulation result. A broadband amplifier of 12.5 GHz 3-dB bandwidth is designed using power constrained optimization technique. The Figure of merit (FOM) of broadband amplifier is 0.4 better when power constrained optimization is applied to the design process. Thus, this new design flow or methodology would provide considerable improvement in reducing design cycle and in increasing the chances of first time right integrated circuit. A fabricated Demodulator prototype was measured and was found to agree with the simulation results. The prototype worked in the region of 190 MHz input frequency and 0-35 MHz output frequency. The prototype had also met the specifications for the W-CDMA hand phone receiver. It achieves EVM of 2.9 %. It also achieved gain ripple of 0.12 dB, gain mismatch of 0.1 dB and phase mismatch of O 25 . 1 . Simulated VCS could provide 2 % current variation across temperature for a current source. Finally, the design consisting of mixers, frequency dividers, buffer amplifiers and bias/control circuits consumes 4 mA with 3 V power supply. The performance of the variable signal generator is verified using Cadence simulation at a supply voltage of 1.8 V. The simulation results indicate that the variable signal generator is able to produce a signal with three center frequencies, i.e. 3.35 GHz, 3.85 GHz and 4.35 GHz at 400 mV peak-to-peak within every 4 ns. The hop between the frequencies is less than 1 ns.