Investigation on pattern based Algorithm for division by a constant number using Verilog code for optimization on the Nelust results - Fouziah Md Yassin; Ag Asri Ag Ibrahim; Zaturrawiah Ali Omar; Saturi Baco (Universiti Malaysia Sabah, 2015)
Even though sophisticated synthesis strategies are used for optimization (e.g. area and power consumption), the quality of the result heavily depends on the quality of the Register Transfer Level (RTL). For multiplication and division by a constant number that is power of 2 can be done using left shift (multiplication) and right shift (division) in RTL design. However systems commonly multiply and divided by other constant numbers, such as by 3 or 7. An implementation of division in hardware is expensive. One of the alternatives is by replacing it with cheaper adder and shifter to compute the same result. The research is to develop an algorithm of unsigned constant division via add-shift method using Verilog code. The result is rounded to the nearest integer for divisors of 3, 5, 6, 7 and 9. The methodology of this research are involving design specification, high level design using C++, RTL level description using Verilog, functional verification and logic synthesis using two different technology library. The required results were obtained. The outputs (div_out) of all denominators (deno) have been rounded to the nearest integer. However, the maximum bit widths of numerators (numerator) are only 13 except for the divisor of 3 that has the maximum bit width up to 16. The synthesis result of area, power and timing shows the Significant difference between O.18\Jm Siltera technology and MIMOS O.351-1m technology library. However, both technologies show the optimization of power and timing for constant division using add-shift scheme.