APA (7th ed.) Citation

Yassin, F. M., Ibrahim, A. A. A., Omar, Z. A., Baco, S., Zakaria, N. A., & Jr, E. V. (2016). Rounded off unsigned constant division using add-shift in verilog.

Chicago Style (17th ed.) Citation

Yassin, Fouziah Md, Ag Asri Ag Ibrahim, Zaturrawiah Ali Omar, Saturi Baco, Nor Azura Zakaria, and Edward V.Bautista Jr. Rounded off Unsigned Constant Division Using Add-shift in Verilog. 2016.

MLA (9th ed.) Citation

Yassin, Fouziah Md, et al. Rounded off Unsigned Constant Division Using Add-shift in Verilog. 2016.