An Experimental Study Of Combinational Logic Circuit Minimization Using Firefly Algorithm - Aznilnda, Zainodin; Aida Khairunisa, Ab. Kadir; M. Nasir, Ayob; Ahmad Fariz, Hasan; Amar Faiz, Zainal Abidin; Fazlinashatul Suhaidah, Zahid; Hazriq Izuan, Jafar; Ismail, Mohd Khairuddin (2014)
Combinatorial logic circuit minimization is usualy done using Karnaugh’s Map or Bolean equation. This paper presents an aplication of Firefly Algorithm to design combinational logic circuit in which the objective function is to minimize the total number of gates used. Then, the algorithm is benchmarked with other literatures. Result indicates that it able to find optimal solution but further analysis is required for a more complex combinatorial ogic circuit minimization