Design of optimal nanoscale channel dimensions of FinFET based on constituent semiconductor materials - Ali, Ahmed Mahmood (2019)
Nano-electronic applications have benefited enormously from the great advancement in the emerging Nano-technology industry. The tremendous downscaling of the transistors’ dimensions has enabled the placement of over 100 million transistors on a single chip thus reduced cost, increased functionality and enhanced performance of integrated circuits (ICs). However, reducing size of the conventional planar transistors would be exceptionally challenging due to leakages electrostatics and other fabrication issues. Fin Field Effect Transistor (FinFET) shows a great potential in scalability and manufacturability as a promising candidate in nanoscale complementary metal-oxidesemiconductor (CMOS) technologies. The structure of FinFET provides superior electrical control over the channel conduction, thus it has attracted widespread interest from researchers in both academia and industry. However, aggressively scaling down of channel dimensions, mainly the channel length, will degrade the overall performance due to detrimental short channel effects (SCEs). The aim of this study is to design optimal Nano-dimensional channel of FinFET based on electrical characteristics and semiconductor material (Si GaAs Ge and InAs) to overcome dimensions shrunk down issues and ensure the best performance of FinFETs. This was achieved by proposing a new scaling factor, K, to simultaneously shrinking the physical scaling limits of channel dimensions for various FinFETs without degrading their performance. A simulationbased comprehensive comparative study depending on FOUR (4) variable parameters: length, width and oxide thickness of channel in addition to scaling factor were carried out. The impact of changing channel dimensions on the performance of each type of FinFETs was evaluated base on FOUR (4) electrical characteristics namely; (i) ION/IOFF ratio (ii) Subthreshold Swing (SS), (iii) Threshold voltage (VT), and (iv) Drain-induced barrier lowering (DIBL). The well-known MuGFET simulation tool for nano-scale multi-gate FET structure is utilized to conduct experimental simulations under the considered conditions. The obtained simulation results showed that the optimal channel dimensions for best performance of all considered FinFETs types were achieved at a minimal scaling factor K = 0.125 with 5 nm length, 2.5 nm width and 0.625 nm oxide thickness of channel. Furthermore, Si-FinFET achieved the highest ION/IOFF ratio (up to 2.12 × 10 8 ) and outperformed GaAs-FinFET, and both maintained a superior performance in terms of ION/IOFF ratio and SS value compared to the other two types of FinFETs. In contrast, the Ge-FinFET performance was degraded and reached the lowest ION/IOFF ratio (2.29 × 10 5 ), whereas the worst characteristics in terms of SS value (94 mV/dec) occurred with InAs-FinFET. The obtained results introduced new limits with enhancing FinFETs performance in terms of the investigated characteristics. The outcomes of this research contribute towards new channel nano scaling limits of FinFETs as potential successors to planar transistors in nanoscale devices and nanotechnology applications, and further analysing the electrical characteristics of FinFETs with reducing leakage current and overcoming SCEs.