Mohd Tarmizi, S. (2013). Analysis and design of a low power, high speed sample and hold circuit for pipelined ADC using 0.18um CMOS technology / Suhaib Mohd Tarmizi.
Chicago Style (17th ed.) CitationMohd Tarmizi, Suhaib. Analysis and Design of a Low Power, High Speed Sample and Hold Circuit for Pipelined ADC Using 0.18um CMOS Technology / Suhaib Mohd Tarmizi. 2013.
MLA (9th ed.) CitationMohd Tarmizi, Suhaib. Analysis and Design of a Low Power, High Speed Sample and Hold Circuit for Pipelined ADC Using 0.18um CMOS Technology / Suhaib Mohd Tarmizi. 2013.
Warning: These citations may not always be 100% accurate.