Investigation of latch-up behaviour in 0.5 micron CMOS technology / Wan Fazldia Hanim, Suhana Sulaiman and Jamil Napiah
The research project investigates available latch-up test structures from MIMOS Berhad and covers current-voltage characterization of silicon-controlled rectifier behaviour of parasitic BJTs in CMOS technology. Measurement setup utilizing the structures for IV measurements are designed. A suitable m...
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| Main Authors: | , , |
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| Format: | Research Reports |
| Language: | en |
| Published: |
2005
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| Subjects: | |
| Online Access: | https://ir.uitm.edu.my/id/eprint/48264/1/48264.pdf https://ir.uitm.edu.my/id/eprint/48264/ |
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| Summary: | The research project investigates available latch-up test structures from MIMOS Berhad and covers current-voltage characterization of silicon-controlled rectifier behaviour of parasitic BJTs in CMOS technology. Measurement setup utilizing the structures for IV measurements are designed. A suitable measurement routine for the testing of latch-up in MOS device engineering at wafer level is developed for use in research environment. Tests are done on available MIMOS test structures representing twin tub technology and silicon-on-insulator substrate using automatic semiconductor characterization system comprising of Semiconductor Parametric Characterization Software (SPECS), UFK200 automatic prober and Agilent 4073 tester. Avalanche induced latch-up of three types of device were demonstrated: SOI without thickness adjustment, SOI with thinner layer due to thickness adjustment and bulk silicon control device are demonstrated. Immunity towards latch-up is improved for devices on BSOI substrate. |
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