Low area Programmable Memory Built-In Self-Test (PMBIST) for small embedded ram cores / Nur Qamarina Mohd Noor - Mohd Noor, Nur Qamarina (2013)
As latest trend in designing processors and system-on-chips (SoCs) requires more RAMs than logics, these embedded RAMs contribute to the high percentage of yields for these processors and SoCs. To ensure high percentage of yield is achieved, a builtin self-test (BIST) is utilized to test these RAMs. The memory BIST applies various test algorithms such as MARCH tests to detect various RAM faults. Numerous design objectives such as programmability, low area overhead, at-speed/full-speed test and multiple RAMs target are proposed in the BIST designs. These objectives must be achieved to provide best fault detection in these embedded RAMs. A technique called clustering which is applied to other architectures such as VLIW processor and FPGA architecture is utilized in this study to achieve low area programmable memory BIST (P-MBIST). Three experiments are performed in this study. The first experiment is performed by clustering test patterns of RAMs under test. The second experiment deeply encodes the clusters of test patterns to improve the cluster technique to allow multiple test data types. The third experiment is performed to concurrently test an array of small embedded RAMs which is developed on a FPGA device. The simulation and synthesis tools used in these experiments are ModelSim, ALTERA’s Quartus II and Synopsys Design Compiler. The FPGA implementation is performed on the Cyclone II FPGA device of ALTERA’s DE2-70 board. It is justified that the cluster technique provides full-speed test and low area overhead for the programmable memory BIST controller. The proposed clustered FSM-based and microcode-based P-MBIST achieves around 15% and 32% of area reduction respectively. This area reduction is further improved in the proposed deep-encoded FSM-based and microcode-based P-MBIST where their areas are around 25% and 44% respectively. The lower and upper nibbles looping in the address generator proves that concurrent test of multiple RAMs target can be achieved.