Simulation of double stack dielectric MOS capacitor: article / Farhatasya Amran
This paper reports the study about the relationship of Capacitance-Voltage (C-V) characteristics in MOS structure devices characterization. All these things are completely related with the experimental of double stack dielectric MOS capacitor in range of 35nm, 65nm and 95nm Silicon Oxide thickness n...
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| Main Author: | |
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| Format: | Article |
| Language: | en |
| Published: |
2013
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| Online Access: | https://ir.uitm.edu.my/id/eprint/115579/1/115579.pdf https://ir.uitm.edu.my/id/eprint/115579/ |
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| Summary: | This paper reports the study about the relationship of Capacitance-Voltage (C-V) characteristics in MOS structure devices characterization. All these things are completely related with the experimental of double stack dielectric MOS capacitor in range of 35nm, 65nm and 95nm Silicon Oxide thickness neither calculated nor simulated capacitance. This project has been done by absolutely using TCAD Silvaco software. Athena and Atlas tools modules are most important simulators used that had been calibrated and manipulated in this experiment in order to fabricate the better MOS Capacitor with the fabricated industry standard sample from wafer Fabrication Lab. For this study, three operating modes under negative and positive bias such as the accumulation, depletion and inversion also have been put to prove the capacitance value obtained. Besides that, few parameters that have been considered and pay more attention which are the dielectric permittivity, thickness of dielectric, and MOS structure’s area in this experiment to relate both of the calculated value and simulation output of the total capacitance from fabricated sample. |
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