Design and analysis of sequence generator module using eulerian path algorithm for DNA fragment assembly / Mustaqim Mohd Subri
This project is to design and analysis the sequence generator module using Eulerian Path algorithm for DNA fragment assembly. Traditionally, “overlap-layoutconsensus” technique is used for DNA fragment assembly, but this technique has a problem in assembling a long sequence of DNA which a new techni...
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| Format: | Student Project |
| Language: | en |
| Published: |
2013
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| Online Access: | https://ir.uitm.edu.my/id/eprint/113949/1/113949.pdf https://ir.uitm.edu.my/id/eprint/113949/ |
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| Summary: | This project is to design and analysis the sequence generator module using Eulerian Path algorithm for DNA fragment assembly. Traditionally, “overlap-layoutconsensus” technique is used for DNA fragment assembly, but this technique has a problem in assembling a long sequence of DNA which a new technique needs to be used to overcome this problem. The main objectives of this project is to design the DNA sequence generator module using the Eulerian Path algorithm. This project is designed based on speed optimization. DNA fragment assembly is a process to reassemble DNA fragments into several others sequence similar to the process of completing a puzzle. The DNA fragment assembly consists of two processes, assembling and alignment. This project is done in two approaches, FPGA design flow and ASIC design flow. For FPGA design flow, RTL schematic, synthesis schematic and simulation are done using Xilinx Vivado software. For ASIC design flow, VCS is used to re-verify the DNASGM module, DC is used to re-synthesis the DNASGM with additional constraints and PT for performing STA on the DNASGM. The average area for normal compile and normal compile with high map and area effort are 413,309.1um2, while for compile ultra is 83,096.06um2. The average dynamic power and leakage power for normal compile and normal compile with high effort in map and area are 159.0887uW and 1.8045mW, while for compile ultra is 99.09uW and 263.54uW. Based on comparison between timing analysis in DC and PT, it can be concluded that this system can be implemented with TC equals to 600ns period. Overall, the objective of this project had been successfully achieved from the implementation on FPGA and ASIC design flow. |
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