Analysis of pipeline ADC performances with different sample and hold circuits: article / Asma Mohd Salleh
s paper present the analysis of pipeline analog-todigital converter (ADC) with different architecture of sample and hold circuits. We focused on the comparison of the 1-bit pipeline ADC performances in term of speed and power using double buffer and double sampling sample and hold (S/H) architecture...
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| Format: | Article |
| Language: | en |
| Published: |
2014
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| Online Access: | https://ir.uitm.edu.my/id/eprint/105258/1/105258.pdf https://ir.uitm.edu.my/id/eprint/105258/ |
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