Designing a digital clock using VHDL / Badrulhisham Baharain

This project paper presents the designing a digital clock using VHDL. The VHDL modelling used are behavioural, structural and register transfer language (RTL) modelling. By using this technique it shortens the design process and produced more efficient and effective circuit. The development of digit...

Full description

Bibliographic Details

Main Author:	Baharain, Badrulhisham
Format:	Thesis
Language:	en
Published:	2005
Subjects:	Application software Code generators
Online Access:	https://ir.uitm.edu.my/id/eprint/102687/1/102687.pdf https://ir.uitm.edu.my/id/eprint/102687/
Tags:	Add Tag No Tags, Be the first to tag this record!