Multiprocessor arbitration for AMBA interface in ASIC - Rokon, M. I. R.; Motakabber, S. M. A.; Zahirul Alam, A. H. M.; Habaebi, Mohamed Hadi; Matin, M. A. (AlamBiblio Publishers, 2021)
This paper addresses the multiprocessor arbitration for any System on Chip or ASIC. Any system, be it simple controller or very supplicated system, it needs processor to operate. There are series of processors offered by Intel, AMD or processor companies. Previously single processor used for any chop to access different targets. But technology advances, industry felt the need of multiprocessor access for higher performance. In order to allow multiprocessor to access it targets, system needs an efficient interface with very sophisticated arbitration system. This paper carried out the research to come up with an improved algorithm of hardware to allow multiprocessor access to the system. In order to design the hardware, modern HDL based design methodology has been used. There are two industry standard HDL by IEEE – VHDL and Verilog. Here Verilog is used. In HDL based d=hardware development, simulation is most important part to very verify design’s functionality and make sure its 100% correct. Otherwise if any design problem goes forward undetected, that’ll cost so much money and time in order to go back and fix, in some cases full respin. For hardware implementation Xilinx FPGA Device has been targeted on this research. AMBA bus protocol used in this research is the industry-standard protocol for processor access and very efficient and straightforward to use with any off the shelf macro available for the high tech industry.