Dynamic power saving for CMOS circuits
With more functionalities being integrated into a microchip today, higher processing power is drawn. As a result of this, clock and logic power consumption has turned out to be a critical issue to be coped with by chip designers. In this paper, we present various power-saving approaches employed in...
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Penerbit Universiti Kebangsaan Malaysia
2024
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| Online Access: | http://journalarticle.ukm.my/25528/1/kejut_6.pdf http://journalarticle.ukm.my/25528/ https://www.ukm.my/jkukm/volume-3604-2024/ |
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| author | Yeap, Kim Ho Ng, Len Luet Ahmad Uzair Mazlan, Loh, Siu Hong Tshai, Kim Hoe |
| author_facet | Yeap, Kim Ho Ng, Len Luet Ahmad Uzair Mazlan, Loh, Siu Hong Tshai, Kim Hoe |
| author_sort | Yeap, Kim Ho |
| building | Tun Sri Lanang Library |
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| content_provider | Universiti Kebangsaan Malaysia |
| content_source | UKM Journal Article Repository |
| continent | Asia |
| country | Malaysia |
| description | With more functionalities being integrated into a microchip today, higher processing power is drawn. As a result of this, clock and logic power consumption has turned out to be a critical issue to be coped with by chip designers. In this paper, we present various power-saving approaches employed in complementary metal oxide semiconductor (CMOS) circuit designs. The approaches involve restructuring the logic circuits, performing clock gating, and selecting the appropriate circuits for counters and frequency divisions. In order to show their efficacies in power optimization, the approaches were applied to a phase-locked loop (PLL), clock divider (CD), full adder (FA), counter, arithmetic logic unit (ALU), and microprocessor without interlocked pipelined stages (MIPS) circuits and validated using Intel Quartus Prime Lite and Mentor Graphics Modelsim. The following conclusions can be drawn from the results: Firstly, the efficacy of minimizing power dissipation using logic restructuring is found to be in direct proportion with the rate of the switching activity (SA); secondly, a maximum of 3.5% of thermal power dissipation can be saved using clock gating; thirdly, gray counters give the lowest power consumption; and, finally, the thermal power estimation for the phase-locked loop (PLL) is relatively higher than that for the clock divider (CD) when both of them are implemented for dividing frequencies. |
| format | Article |
| id | my-ukm.journal.25528 |
| institution | Universiti Kebangsaan Malaysia |
| language | en |
| publishDate | 2024 |
| publisher | Penerbit Universiti Kebangsaan Malaysia |
| record_format | eprints |
| spelling | my-ukm.journal.255282025-07-14T07:49:10Z http://journalarticle.ukm.my/25528/ Dynamic power saving for CMOS circuits Yeap, Kim Ho Ng, Len Luet Ahmad Uzair Mazlan, Loh, Siu Hong Tshai, Kim Hoe With more functionalities being integrated into a microchip today, higher processing power is drawn. As a result of this, clock and logic power consumption has turned out to be a critical issue to be coped with by chip designers. In this paper, we present various power-saving approaches employed in complementary metal oxide semiconductor (CMOS) circuit designs. The approaches involve restructuring the logic circuits, performing clock gating, and selecting the appropriate circuits for counters and frequency divisions. In order to show their efficacies in power optimization, the approaches were applied to a phase-locked loop (PLL), clock divider (CD), full adder (FA), counter, arithmetic logic unit (ALU), and microprocessor without interlocked pipelined stages (MIPS) circuits and validated using Intel Quartus Prime Lite and Mentor Graphics Modelsim. The following conclusions can be drawn from the results: Firstly, the efficacy of minimizing power dissipation using logic restructuring is found to be in direct proportion with the rate of the switching activity (SA); secondly, a maximum of 3.5% of thermal power dissipation can be saved using clock gating; thirdly, gray counters give the lowest power consumption; and, finally, the thermal power estimation for the phase-locked loop (PLL) is relatively higher than that for the clock divider (CD) when both of them are implemented for dividing frequencies. Penerbit Universiti Kebangsaan Malaysia 2024-07 Article PeerReviewed application/pdf en http://journalarticle.ukm.my/25528/1/kejut_6.pdf Yeap, Kim Ho and Ng, Len Luet and Ahmad Uzair Mazlan, and Loh, Siu Hong and Tshai, Kim Hoe (2024) Dynamic power saving for CMOS circuits. Jurnal Kejuruteraan, 36 (4). pp. 1399-1407. ISSN 0128-0198 https://www.ukm.my/jkukm/volume-3604-2024/ |
| spellingShingle | Yeap, Kim Ho Ng, Len Luet Ahmad Uzair Mazlan, Loh, Siu Hong Tshai, Kim Hoe Dynamic power saving for CMOS circuits |
| title | Dynamic power saving for CMOS circuits |
| title_full | Dynamic power saving for CMOS circuits |
| title_fullStr | Dynamic power saving for CMOS circuits |
| title_full_unstemmed | Dynamic power saving for CMOS circuits |
| title_short | Dynamic power saving for CMOS circuits |
| title_sort | dynamic power saving for cmos circuits |
| url | http://journalarticle.ukm.my/25528/1/kejut_6.pdf http://journalarticle.ukm.my/25528/ https://www.ukm.my/jkukm/volume-3604-2024/ |
| url_provider | http://journalarticle.ukm.my/ |