Search Results - Norina, Idris

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  1. 1
    8-bits X 8-bits modified Booth 1’s complement multiplier

    8-bits X 8-bits modified Booth 1’s complement multiplier by Norafiza Salehan

    Published 2008
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  2. 2
    High speed six operands 16-bits carry save adder

    High speed six operands 16-bits carry save adder by Awatif Hashim

    Published 2008
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  3. 3
    16-Bits Carry Look-Ahead Adder as a High Speed Adder

    16-Bits Carry Look-Ahead Adder as a High Speed Adder by Normala Muhd. Hussain

    Published 2008
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  4. 4
    The memory-less method of generating multiplicative inverse values for S-box in AES algorithm

    The memory-less method of generating multiplicative inverse values for S-box in AES algorithm by Siti Zarina, Md Naziri, Norina, Idris

    Published 2009
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  5. 5
    Comparison of Speed on 5 Adder Architectures

    Comparison of Speed on 5 Adder Architectures by Norina Mohd Yusoff

    Published 2008
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  6. 6
    16-Bits High Speed Carry Select Adder

    16-Bits High Speed Carry Select Adder by Nur Syuhada Muhammad Khariri

    Published 2008
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  7. 7
    High speed 8-bits x 8-bits Wallace Tree multiplier

    High speed 8-bits x 8-bits Wallace Tree multiplier by Tajul Hamimi Harun

    Published 2008
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  8. 8
    An efficient modified booth multiplier architecture

    An efficient modified booth multiplier architecture by Razaidi, Hussin, Ali Yeon, Md Shakaff, Prof. Dr., Norina, Idris, Zaliman, Sauli, Prof. Dr., Rizalafande, Che Ismail, Afzan, Kamarudin

    Published 2012
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