Search Results - Fujiwara, Hideo

Hideo Fujiwara

is a Japanese computer scientist who made significant contributions to ATPG (automatic test pattern generation) algorithms. As one of his works, he invented the FAN algorithm in 1983, which was the fastest ATPG algorithm at that time, and was adopted by industry.

He was born in Nara, Japan, and studied electronic engineering at Osaka University, where he received his B.E. degree in 1969, M.E. in 1971, and Ph.D. in 1974. He was with Osaka University from 1974 to 1985, Meiji University from 1985 to 1993, Nara Institute of Science and Technology (NAIST) from 1993 to 2011, and Osaka Gakuin University from 2011 to 2021. Presently, he is Professor Emeritus of NAIST. Provided by Wikipedia
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  1. 1
    Power-Conscious Microprocessor-Based Testing of System-on-Chip

    Power-Conscious Microprocessor-Based Testing of System-on-Chip by Hussin, Fawnizu Azmadi, Yoneda, Tomokazu, Orailoglu, Alex, Fujiwara, Hideo

    Published 2006
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  2. 2
    NoC Wrapper Optimization under Channel Bandwidth and Test Time Constraints

    NoC Wrapper Optimization under Channel Bandwidth and Test Time Constraints by Hussin, Fawnizu Azmadi, Yoneda, Tomokazu, Fujiwara, Hideo

    Published 2007
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  3. 3
    Core-Based Testing of System-on-Chips Utilizing the Network-on-Chip Resources

    Core-Based Testing of System-on-Chips Utilizing the Network-on-Chip Resources by Hussin, Fawnizu Azmadi, Yoneda, Tomokazu, Fujiwara, Hideo

    Published 2008
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  4. 4
    A new class of sequential circuits with acyclic test generation complexity

    A new class of sequential circuits with acyclic test generation complexity by Ooi, Chia Yee, Fujiwara, Hideo

    Published 2006
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  5. 5
    Area Overhead and Test Time Co-Optimization through NoC Bandwidth Sharing

    Area Overhead and Test Time Co-Optimization through NoC Bandwidth Sharing by Hussin, Fawnizu Azmadi, Yoneda, Tomokazu, Fujiwara, Hideo

    Published 2007
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  6. 6
    Core-Based Testing of Multiprocessor System-on-Chips Utilizing Hierarchical Functional Buses

    Core-Based Testing of Multiprocessor System-on-Chips Utilizing Hierarchical Functional Buses by Hussin, Fawnizu Azmadi, Yoneda, Tomokazu, Orailoglu, Alex, Fujiwara, Hideo

    Published 2007
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  7. 7
    Optimization of NoC Wrapper Design Under Bandwidth and Test Time Constraints

    Optimization of NoC Wrapper Design Under Bandwidth and Test Time Constraints by Hussin, Fawnizu Azmadi, Yoneda, Tomokazu, Fujiwara, Hideo

    Published 2007
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  8. 8
    Power-Constrained SOC Test Schedules through Utilization of Functional Buses

    Power-Constrained SOC Test Schedules through Utilization of Functional Buses by Hussin, Fawnizu Azmadi, Yoneda, Tomokazu, Orailoglu, Alex, Fujiwara, Hideo

    Published 2006
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  9. 9
    A new scan design technique based on pre-synthesis thru functions

    A new scan design technique based on pre-synthesis thru functions by Chia, Yee Ooi, Fujiwara, Hideo

    Published 2006
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  10. 10
    RedSOCs‐3D: Thermal‐safe Test Scheduling for 3D‐Stacked SoC

    RedSOCs‐3D: Thermal‐safe Test Scheduling for 3D‐Stacked SoC by Hussin, Fawnizu Azmadi, Yu, Thomas Edison Chua, Yoneda, Tomokazu, Fujiwara, Hideo

    Published 2010
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  11. 11
    Scheduling Power-Constrained Tests through the SoC Functional Bus

    Scheduling Power-Constrained Tests through the SoC Functional Bus by Hussin, Fawnizu Azmadi, Yoneda, Tomokazu, Orailoglu, Alex, Fujiwara, Hideo

    Published 2008
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  12. 12
    On NoC Bandwidth Sharing for the Optimization of Area Cost and Test Application Time

    On NoC Bandwidth Sharing for the Optimization of Area Cost and Test Application Time by Hussin, Fawnizu Azmadi, Yoneda, Tomokazu, Fujiwara, Hideo

    Published 2008
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  13. 13
    NoC-Compatible Wrapper Design and Optimization under Channel-Bandwidth and Test-Time Constraints

    NoC-Compatible Wrapper Design and Optimization under Channel-Bandwidth and Test-Time Constraints by Hussin, Fawnizu Azmadi, Yoneda, Tomokazu, Fujiwara, Hideo

    Published 2008
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