Search Results - 57201289731

Statistical process modelling for 32nm high-K/metal gate PMOS device by Maheran A.H.A., Noor Faizah Z.A., Menon P.S., Ahmad I., Apte P.R., Kalaivani T., Salehuddin F.

Effect of process parameter variability on the threshold voltage of downscaled 22nm PMOS using taguchi method by Maheran A.H.A., Menon P.S., Shaari S., Kalaivani T., Ahmad I., Faizah Z.A.N., Apte P.R.

Analysis of threshold voltage variance in 45nm n-channel device using L27 orthogonal array method by Salehuddin F., Mohd Zain A.S., Idris N.M., Mat Yamin A.K., Abdul Hamid A.M., Ahmad I., Menon P.S.

Statistical modelling of 14nm n-types MOSFET by Noor Faizah Z.A., Ahmad I., Ker P.J., Siti Munirah Y., Mohd Firdaus R., Mah S.K., Menon P.S.

Optimization of process parameters for threshold voltage and leakage current based on taguchi method by Noor Faizah Z.A., Ahmad I., Ker P.J., Menon P.S., Afifah Maheran A.H., Mah S.K.

Robust optimization of a silicon lateral pin photodiode by Kalthom Tasirin S., Susthitha Menon P., Ahmad I., Fazlili Abdullah S.

Optimisation of process parameters for lower leakage current in 22 nm n-type MOSFET device using Taguchi method by Afifah Maheran A.H., Menon P.S., Ahmad I., Shaari S.

Optimisation of process parameters for lower leakage current in 22 nm n-type MOSFET device using Taguchi method by Afifah Maheran A.H., Menon P.S., Ahmad I., Shaari S.

Process parameters optimization of 14nm p-type MOSFET using 2-D analytical modeling by Noor Faizah Z.A., Ahmad I., Ker P.J., Siti Munirah Y., Mohd Firdaus R., Mah S.K., Menon P.S.

Vth and ILEAK Optimization using taguchi method at 32nm bilayer graphene PMOS by Noor Faizah Z.A., Ahmad I., Ker P.J., Menon P.S., Afifah Maheran A.H.

Bandgap shifting and crystalline quality of rf-sputtered intrinsic-zno nanofilm for tfsc application by Husna J., Menon P.S., Chelvanathan P., Sampe J., Amin N., Tripathy S.K., Lenka T.R., Md. Zain A.R., Mohamed M.A.

Design and optimization of 22nm NMOS transistor by Afifah Maheran A.H., Menon P.S., Ahmad I., Shaari S., Elgomati H.A., Majlis B.Y., Salehuddin F.

Scaling down of the 32 nm to 22 nm gate length NMOS transistor by Afifah Maheran A.H., Menon P.S., Ahmad I., Elgomati H.A., Majlis B.Y., Salehuddin F.

High performance silicon lateral PIN photodiode by Tasirin S.K., Menon P.S., Ahmad I., Abdullah S.F.

Taguchi optimization of a SiGe/Si quantum dot SOI-based lateral PIN photodiode by Menon P.S., Tasirin S.K., Ahmad I., Abdullah S.F.

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Application of Taguchi method in designing a 22nm high-k/metal gate NMOS transistor by Afifah Maheran A.H., Menon P.S., Ahmad I., Shaari S.

Effect of Halo structure variations on the threshold voltage of a 22 nm gate length NMOS transistor by Afifah Maheran A.H., Menon P.S., Ahmad I., Shaari S.

Responsivity optimization of a MQW SOI-based lateral PIN photodiode using Taguchi's L27 orthogonal array by Menon P.S., Tasirin S.K., Ahmad I., Abdullah S.F., Apte P.R.

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Wide wavelength range and high speed SiGe/Si multi quantum-well silicon-on-insulator-based lateral PIN photodiode by Menon P.S., Tasirin S.K., Ahmad I., Abdullah S.F.

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Statistical optimization of process parameters for threshold voltage in 22 nm p-Type MOSFET using Taguchi method by Maheran A.H.A., Menon P.S., Shaari S., Ahmad I., Faizah Z.A.N.