Simulation of carbon nanotube based D-flip-flop for counter application
Carbon Nanotube (CNT) has been aggressively researched due to its potential use in numbers of electronics application. In this work, 32-nm technology Carbon Nanotube Field Effect Transistor (CNTFET) was used to simulate the DFlip- flop (D-FF) circuit which is then implemented in synchronous up – cou...
保存先:
| 主要な著者: | , , , , , |
|---|---|
| フォーマット: | Conference or Workshop Item |
| 出版事項: |
2023
|
| 主題: | |
| オンライン･アクセス: | http://eprints.utm.my/107686/ http://dx.doi.org/10.1109/SENNANO57767.2023.10352540 |
| タグ: |
タグ追加
タグなし, このレコードへの初めてのタグを付けませんか!
|
| 要約: | Carbon Nanotube (CNT) has been aggressively researched due to its potential use in numbers of electronics application. In this work, 32-nm technology Carbon Nanotube Field Effect Transistor (CNTFET) was used to simulate the DFlip- flop (D-FF) circuit which is then implemented in synchronous up – counter circuit. The number of transistor count was minimized using Pass transistor logic (PTL) approach. The performance was evaluated based on the propagation delay, average power, power-delay product (PDP), and energy delay product (EDP). The supply voltage, VDD and the CNT diameter were varied. Result obtains indicate notable effect by VDD particularly on the average power and propagation delay. Although smaller CNT diameter was found to lower the propagation delay, it traded of with the power consumption. The outcome of this study provides another evident on CNT nanomaterial for implementation in future nanoelectronics application. |
|---|