An improved readout topology of resistive sensor array for reduced measurement error
Readout circuit integrated with large scale sensors array is important for improving the effectiveness of data acquisition system. However to design such system, it will require a variety of additional components which contributes to the increment of power consumption. In this paper we proposed an i...
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| Main Authors: | , , , |
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| 格式: | Conference or Workshop Item |
| 語言: | English |
| 出版: |
IEEE
2015
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| 在線閱讀: | http://psasir.upm.edu.my/id/eprint/48252/1/An%20improved%20readout%20topology%20of%20resistive%20sensor%20array%20for%20reduced%20measurement%20error.pdf http://psasir.upm.edu.my/id/eprint/48252/ |
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| 總結: | Readout circuit integrated with large scale sensors array is important for improving the effectiveness of data acquisition system. However to design such system, it will require a variety of additional components which contributes to the increment of power consumption. In this paper we proposed an improved method of readout topology for resistive sensor array to reduce the measurement error. A new equation is also proposed to obtain the resistance value. A simulation has been done on 8×8 matrix sensor array represented by 64 fixed resistors and 8 standard reference resistors. The results show that the optimum reference resistance is 510 Ω for the value range between 100 Ω and 100 kΩ, and the improved percentage error is kept to be lower than 5%. |
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