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Application of Taguchi method in the optimization of process variation for 32nm CMOS technology

In this paper, we investigate the effect of four process parameters namely HALO implantation, compensation implantations, SiO2 thickness and silicide annealing time on threshold voltage (VTH) in complementary metal oxide semiconductor (CMOS) technology. The setting of process parameters were determi...

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Main Authors: Elgomati, H.A., Majlis, B.Y., Ahmad, I., Salehuddin, F., Hamid, F.A., Zaharim, A., Apte, P.R.
Format: Article
Published: 2017
Online Access:http://dspace.uniten.edu.my:80/jspui/handle/123456789/5239
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spelling my.uniten.dspace-52392018-03-02T03:26:42Z Application of Taguchi method in the optimization of process variation for 32nm CMOS technology Elgomati, H.A. Majlis, B.Y. Ahmad, I. Salehuddin, F. Hamid, F.A. Zaharim, A. Apte, P.R. In this paper, we investigate the effect of four process parameters namely HALO implantation, compensation implantations, SiO2 thickness and silicide annealing time on threshold voltage (VTH) in complementary metal oxide semiconductor (CMOS) technology. The setting of process parameters were determined by Taguchi method in experimental design. The influence of the main process parameters on threshold voltage were determined using analysis of variance (ANOVA). The fabrication processes of the transistor were performed by a simulator namely ATHENA. The electrical characterization of the device was done by the a simulator of ATLAS. These two simulators were combined with Taguchi method to aid in design and optimizing process parameters. The other two parameter used in this experiments were Source/Drain (S/D) implantation dose and, silicide annealing temperature Threshold voltage (Vth) results were used as the evaluation parameters. The results show that the VTH value of 0.10308V and -0.10319V for NMOS and PMOS respectively. As conclusion, by utilizing Taguchi Method shown that process parameters can adjust threshold voltage (VTH) to a stable value of 0.103V that is well within ITRS prediction for 32nm transistor. 2017-11-15T02:56:56Z 2017-11-15T02:56:56Z 2011 Article http://dspace.uniten.edu.my:80/jspui/handle/123456789/5239
institution Universiti Tenaga Nasional
building UNITEN Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Tenaga Nasional
content_source UNITEN Institutional Repository
url_provider http://dspace.uniten.edu.my/
description In this paper, we investigate the effect of four process parameters namely HALO implantation, compensation implantations, SiO2 thickness and silicide annealing time on threshold voltage (VTH) in complementary metal oxide semiconductor (CMOS) technology. The setting of process parameters were determined by Taguchi method in experimental design. The influence of the main process parameters on threshold voltage were determined using analysis of variance (ANOVA). The fabrication processes of the transistor were performed by a simulator namely ATHENA. The electrical characterization of the device was done by the a simulator of ATLAS. These two simulators were combined with Taguchi method to aid in design and optimizing process parameters. The other two parameter used in this experiments were Source/Drain (S/D) implantation dose and, silicide annealing temperature Threshold voltage (Vth) results were used as the evaluation parameters. The results show that the VTH value of 0.10308V and -0.10319V for NMOS and PMOS respectively. As conclusion, by utilizing Taguchi Method shown that process parameters can adjust threshold voltage (VTH) to a stable value of 0.103V that is well within ITRS prediction for 32nm transistor.
format Article
author Elgomati, H.A.
Majlis, B.Y.
Ahmad, I.
Salehuddin, F.
Hamid, F.A.
Zaharim, A.
Apte, P.R.
spellingShingle Elgomati, H.A.
Majlis, B.Y.
Ahmad, I.
Salehuddin, F.
Hamid, F.A.
Zaharim, A.
Apte, P.R.
Application of Taguchi method in the optimization of process variation for 32nm CMOS technology
author_facet Elgomati, H.A.
Majlis, B.Y.
Ahmad, I.
Salehuddin, F.
Hamid, F.A.
Zaharim, A.
Apte, P.R.
author_sort Elgomati, H.A.
title Application of Taguchi method in the optimization of process variation for 32nm CMOS technology
title_short Application of Taguchi method in the optimization of process variation for 32nm CMOS technology
title_full Application of Taguchi method in the optimization of process variation for 32nm CMOS technology
title_fullStr Application of Taguchi method in the optimization of process variation for 32nm CMOS technology
title_full_unstemmed Application of Taguchi method in the optimization of process variation for 32nm CMOS technology
title_sort application of taguchi method in the optimization of process variation for 32nm cmos technology
publishDate 2017
url http://dspace.uniten.edu.my:80/jspui/handle/123456789/5239
_version_ 1644493624932564992
score 13.222552

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