Statistical process modelling for 32nm high-K/metal gate PMOS device
The evolution of MOSFET technology has been governed solely by device scaling, delivered an ever-increasing transistor density through Moore's Law. In this paper, the design, fabrication and characterization of 32nm HfO2/TiSi2 PMOS device is presented; replacing the conventional SiO2 dielectric...
Saved in:
Main Authors: | Maheran, A.H.A., Noor Faizah, Z.A., Menon, P.S., Ahmad, I., Apte, P.R., Kalaivani, T., Salehuddin, F. |
---|---|
Format: | |
Published: |
2017
|
Online Access: | http://dspace.uniten.edu.my:8080/jspui/handle/123456789/5212 |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Similar Items
-
Statistical process modelling for 32nm high-K/metal gate PMOS device
by: Maheran A.H.A., et al.
Published: (2023) -
Effect of process parameter variability on the threshold voltage of downscaled 22nm PMOS using taguchi method
by: Maheran, A.H.A., et al.
Published: (2017) -
Effect of process parameter variability on the threshold voltage of downscaled 22nm PMOS using taguchi method
by: Maheran A.H.A., et al.
Published: (2023) -
Vth and ILEAK Optimization using taguchi method at 32nm bilayer graphene PMOS
by: Noor Faizah, Z.A., et al.
Published: (2017) -
Vth and ILEAK Optimization using taguchi method at 32nm bilayer graphene PMOS
by: Noor Faizah Z.A., et al.
Published: (2023)