FPGA based Twofish Algorithm
This paper presents the architecture of Twofish algorithm implemented with field programmable gate array (FPGA). Twofish is one of the five finalists in AES contest. It is a 128-bit block cipher and can operate with variable key lengths of 128, 192 and 256 bits. This project only focused on 128 bits...
保存先:
| 主要な著者: | , , , |
|---|---|
| フォーマット: | Working Paper |
| 言語: | English |
| 出版事項: |
Universiti Malaysia Perlis
2009
|
| 主題: | |
| オンライン･アクセス: | http://dspace.unimap.edu.my/xmlui/handle/123456789/6231 |
| タグ: |
タグ追加
タグなし, このレコードへの初めてのタグを付けませんか!
|