SHAHEEN, A. (2017). PATH DELAY DESIGN-FOR-TESTABILITY USING SNOOPING FOR FUNCTIONAL REGISTER-TRANSFER LEVEL CIRCUITS.
シカゴスタイル引用形SHAHEEN, ATEEQ-UR-REHMAN. PATH DELAY DESIGN-FOR-TESTABILITY USING SNOOPING FOR FUNCTIONAL REGISTER-TRANSFER LEVEL CIRCUITS. 2017.
MLA引用形式SHAHEEN, ATEEQ-UR-REHMAN. PATH DELAY DESIGN-FOR-TESTABILITY USING SNOOPING FOR FUNCTIONAL REGISTER-TRANSFER LEVEL CIRCUITS. 2017.
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